M4A5-128/64-12VNI Lattice, M4A5-128/64-12VNI Datasheet - Page 39

• Manufacturer Part Number: M4A5-128/64-12VNI
• Description: CPLD - Complex Programmable Logic Devices HI PERF E2CMOS PLD
• Manufacturer: Lattice

Specifications of M4A5-128/64-12VNI

• Number Of Macrocells: 128
• Number Of Product Terms Per Macro: 20
• Maximum Operating Frequency: 83.3 MHz
• Delay Time: 5 ns
• Number Of Programmable I/os: 160
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: TQFP-100
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Circuit Type: Electrically Erasable
• Logic Function: Programmable
• Logic Type: CMOS
• Package Type: TQFP-100
• Special Features: High Speed, In-System Programmability
• Temperature, Operating, Range: -40 to +85 °C
• Voltage, Supply: 3 to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES
Input Register Delays with ZHT Option:
t
t
Input Latch Delays with ZHT Option:
t
t
t
Zi
Output Delays:
t
t
t
t
Power Delay:
t
Reset and Preset Delays:
t
t
t
t
Clock/LE Width:
t
t
t
t
t
t
t
t
t
SIRZ
HIRZ
SILZ
HILZ
PDIL
BUF
SLW
EA
ER
PL
SRi
SR
SRR
SRW
WLS
WHS
WLA
WHA
GWS
GWA
WIRL
WIRH
WIL
Input register setup time - ZHT
Input register hold time - ZHT
Input latch setup time - ZHT
Input latch hold time - ZHT
Transparent input latch to internal
feedback - ZHT
Output buffer delay
Slow slew rate delay adder
Output enable time
Output disable time
Power-down mode delay adder
Asynchronous reset or preset to internal
register output
Asynchronous reset or preset to register
output
Asynchronous reset and preset register
recovery time
Asynchronous reset or preset width
Global clock width low
Global clock width high
Product term clock width low
Product term clock width high
Global gate width low (for low
transparent) or high (for high
transparent)
Product term gate width low (for low
transparent) or high (for high
transparent)
Input register clock width low
Input register clock width high
Input latch gate width
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
6.0
0.0
6.0
0.0
7.0
7.0
2.0
2.0
3.0
3.0
4.0
4.0
3.0
3.0
4.0
-5
6.0
1.5
2.5
7.5
7.5
2.5
7.5
9.0
6.0
0.0
6.0
0.0
7.0
7.0
2.0
2.0
3.0
3.0
4.0
4.0
3.0
3.0
4.0
ispMACH 4A Family
-55
6.0
1.5
2.5
7.5
7.5
2.5
7.7
9.2
6.0
0.0
6.0
0.0
7.5
8.0
2.5
2.5
3.5
3.5
4.5
4.5
3.5
3.5
4.5
-6
10.0
6.0
1.8
2.5
8.5
8.5
2.5
8.0
6.0
0.0
6.0
0.0
7.5
8.0
2.5
2.5
3.5
3.5
4.5
4.5
3.5
3.5
4.5
-65
10.0
6.0
2.0
2.5
8.5
8.5
2.5
8.0
10.0
6.0
0.0
6.0
0.0
8.0
3.0
3.0
4.0
4.0
5.0
5.0
4.0
4.0
5.0
-7
12.0
6.0
2.5
2.5
9.5
9.5
2.5
9.5
10.0
6.0
0.0
6.0
0.0
8.0
4.0
4.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
-10
10.0
10.0
11.0
14.0
6.0
3.0
2.5
2.5
10.0
12.0
6.0
0.0
6.0
0.0
5.0
5.0
8.0
8.0
6.0
6.0
6.0
6.0
6.0
-12
12.0
12.0
13.0
16.0
6.0
3.0
2.5
2.5
1
15.0
15.0
6.0
0.0
6.0
0.0
6.0
6.0
9.0
9.0
6.0
9.0
6.0
6.0
6.0
-14
15.0
15.0
16.0
19.0
6.0
3.0
2.5
2.5
Unit
39
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns