LCMXO1200C-3TN100I Lattice, LCMXO1200C-3TN100I Datasheet - Page 26
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LCMXO1200C-3TN100I
Manufacturer Part Number
LCMXO1200C-3TN100I
Description
CPLD - Complex Programmable Logic Devices 1200 LUTs 73 I/O 1.8/2.5/3.3V IND
Manufacturer
Lattice
Datasheet
1.LCMXO640C-3TN100I.pdf
(96 pages)
Specifications of LCMXO1200C-3TN100I
Memory Type
SRAM
Number Of Macrocells
600
Delay Time
5.1 ns
Number Of Programmable I/os
73
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Supply Current
21 mA
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Package / Case
TQFP-100
Mounting Style
SMD/SMT
Supply Voltage (max)
3.465 V
Supply Voltage (min)
1.71 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO1200C-3TN100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Figure 2-22. MachXO Configuration and Programming
Density Shifting
The MachXO family has been designed to enable density migration in the same package. Furthermore, the archi-
tecture ensures a high success rate when performing design migration from lower density parts to higher density
parts. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a
lower density device. However, the exact details of the final resource utilization will impact the likely success in
each case.
Port
Mode
Program in seconds
Memory Space
Non-Volatile
Background
ISP 1149.1 TAP Port
microseconds
Download in
Power-up
Refresh
2-23
SRAM Memory
Space
1532
MachXO Family Data Sheet
Configure in milliseconds
Architecture