LC4256ZC-75TN100C Lattice, LC4256ZC-75TN100C Datasheet - Page 28

• Manufacturer Part Number: LC4256ZC-75TN100C
• Description: CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
• Manufacturer: Lattice

Specifications of LC4256ZC-75TN100C

• Memory Type: EEPROM
• Number Of Macrocells: 256
• Number Of Product Terms Per Macro: 80
• Maximum Operating Frequency: 200 MHz
• Delay Time: 4.5 ns
• Number Of Programmable I/os: 48
• Operating Supply Voltage: 1.8 V
• Supply Current: 0.341 mA
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-100
• Mounting Style: SMD/SMT
• Supply Voltage (max): 1.9 V
• Supply Voltage (min): 1.7 V
• Package: 100TQFP
• Family Name: ispMACH® 4000Z
• Number Of Macro Cells: 256
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 64
• Number Of Logic Blocks/elements: 36
• Typical Operating Supply Voltage: 1.8 V
• Operating Temperature: 0 to 90 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispMACH 4000V/B/C Internal Timing Parameters (Cont.)
t
t
t
Control Delays
t
t
t
t
t
t
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.
PDLi
SRi
SRR
BCLK
PTCLK
BSR
PTSR
GPTOE
PTOE
Parameter
Propagation Delay through
Transparent Latch to Output/
Feedback MUX
Asynchronous Reset or Set to
Output/Feedback MUX Delay
Asynchronous Reset or Set
Recovery Time
GLB PT Clock Delay
Macrocell PT Clock Delay
Block PT Set/Reset Delay
Macrocell PT Set/Reset Delay
Global PT OE Delay
Macrocell PT OE Delay
Description
Over Recommended Operating Conditions
0.28
1.67
—
—
—
—
—
—
—
-2.5
0.25
1.12
0.87
1.83
1.11
2.83
1.83
28
—
—
ispMACH 4000V/B/C/Z Family Data Sheet
0.28
1.67
—
—
—
—
—
—
—
-2.7
0.25
1.12
0.87
1.83
1.41
4.13
2.13
—
—
0.28
1.67
—
—
—
—
—
—
—
-3
0.25
1.12
0.87
1.83
1.51
5.33
2.33
—
—
0.28
1.67
—
—
—
—
—
—
—
-3.5
0.25
1.12
0.87
1.83
1.61
5.33
2.83
—
—
Timing v.3.2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns