LC4256ZC-75TN100C Lattice, LC4256ZC-75TN100C Datasheet - Page 4

CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD

LC4256ZC-75TN100C

Manufacturer Part Number
LC4256ZC-75TN100C
Description
CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
Manufacturer
Lattice
Datasheet

Specifications of LC4256ZC-75TN100C

Memory Type
EEPROM
Number Of Macrocells
256
Number Of Product Terms Per Macro
80
Maximum Operating Frequency
200 MHz
Delay Time
4.5 ns
Number Of Programmable I/os
48
Operating Supply Voltage
1.8 V
Supply Current
0.341 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-100
Mounting Style
SMD/SMT
Supply Voltage (max)
1.9 V
Supply Voltage (min)
1.7 V
Package
100TQFP
Family Name
ispMACH® 4000Z
Number Of Macro Cells
256
Maximum Propagation Delay Time
7.5 ns
Number Of User I/os
64
Number Of Logic Blocks/elements
36
Typical Operating Supply Voltage
1.8 V
Operating Temperature
0 to 90 °C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LC4256ZC-75TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Figure 2. Generic Logic Block
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.
Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
Array.
from GRP
36 Inputs
4
Generator
Clock
ispMACH 4000V/B/C/Z Family Data Sheet
To GRP
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
Output Enable
Product Term
Sharing
To

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