A2F200M3F-1FGG484 Actel, A2F200M3F-1FGG484 Datasheet - Page 108

• Manufacturer Part Number: A2F200M3F-1FGG484
• Description: FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
• Manufacturer: Actel

Specifications of A2F200M3F-1FGG484

• Processor Series: A2F200
• Core: ARM Cortex M3
• Number Of Logic Blocks: 8
• Maximum Operating Frequency: 120 MHz
• Number Of Programmable I/os: 161
• Data Ram Size: 4608 bit
• Delay Time: 200 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 200000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SmartFusion Programming
In-Application Programming
4 - 6
The JTAGSEL pin selects the FPGA TAP controller or the Cortex-M3 debug logic. When JTAG SEL is
asserted, the FPGA TAP controller is selected and the TRSTB input into the Cortex-M3 is held in a reset
state (logic 0), as depicted in
Note:
Figure 4-1 • TRSTB Logic
In-application programming refers to the ability to reprogram the various flash areas under direct
supervision of the Cortex-M3.
Reprogramming the FPGA Fabric Using the Cortex-M3
In this mode, the Cortex-M3 is executing the programming algorithm on-chip. The IAP driver can be
incorporated into the design project and executed from eNVM or eSRAM. The SoC Products Group
provides working example projects for SoftConsole, IAR, and Keil development environments. These
can be downloaded via the SoC Products Group Firmware Catalog. The new bitstream to be
programmed into the FPGA can reside on the user’s printed circuit board (PCB) in a separate SPI flash
memory. Alternately, the user can modify the existing projects supplied by the SoC Products Group and,
via custom handshaking software, throttle the download of the new image and program the FPGA a
piece at a time in real time. A cost-effective and reliable approach would be to store the bitstream in an
external SPI flash. Another option is storing a redundant bitstream image in an external SPI flash and
loading the newest version into the FPGA only when receiving an IAP command. Since the FPGA I/Os
are tristated or held at predefined or last known state during FPGA programming, the user must use MSS
I/Os to interface to external memories. Since there are two SPI controllers in the MSS, the user can
dedicate one to an SPI flash and the other to the particulars of an application. The amount of flash
memory required to program the FPGA always exceeds the size of the eNVM block that is on-chip. The
external memory controller (EMC) cannot be used as an interface to a memory device for storage of a
bitstream because its I/O pads are FPGA I/Os; hence they are tristated when the FPGA is in a
programming state.
JTAG_SEL
Standard ARM JTAG connectors do not have access to the JTAGSEL pin. SoC Product Group’s
free Eclipse-based IDE, SoftConsole, automatically selects the appropriate TAP controller using
the CTXSELECT JTAG command. When using SoftConsole, the state of JTAGSEL is a "don't
care."
VJTAG (1.5 V to 3.3. V nominal)
TRSTB
Figure
4-1. Users should tie the JTAGSEL pin high externally.
R e vi s i o n 6
TRSTB
FPGA TAP
Controller
Controller
TAP
Programming Control
Cortex-M3
FPGA