AGLP030V5-CSG289 Actel, AGLP030V5-CSG289 Datasheet - Page 122

• Manufacturer Part Number: AGLP030V5-CSG289
• Description: FPGA - Field Programmable Gate Array 30K System Gates
• Manufacturer: Actel

Specifications of AGLP030V5-CSG289

• Processor Series: AGLP030
• Core: IP Core
• Number Of Macrocells: 256
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 4
• Data Ram Size: 4608 bit
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 30 K
• Package / Case: CSP-289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet Information
4- 2
Revision
Revision 11 (continued) The values in the following tables were updated. 3.3 V LVCMOS and 1.2 V
LVCMOS wide range were added to the tables where applicable.
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software
Settings
Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software
Settings1
Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions—Software Default Settings
Table 2-22 • Summary of Maximum and Minimum DC Input Levels
Table 2-23 • Summary of AC Measuring Points
Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings,
STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC =
1.425 V, Worst-Case VCCI = 3.0 V
Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings,
STD Speed Grade Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC =
1.14 V, Worst-Case VCCI = 3.0 V
Table 2-28 • I/O Output Buffer Maximum Resistances 1
A table note was added to
Static Power Consumption in IGLOO PLUS Devices
Components Contributing to the Static Power Consumption in IGLOO PLUS
Devices
operating at lowest frequency.
Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances
addition of 3.3 V and 1.2 V LVCMOS wide range. The notes defining R
UP-MAX
Table 2-30 • I/O Short Currents IOSH/IOSL
and 1.2 V LVCMOS wide range (SAR 79353 and SAR 79366).
Table 2-31 • Duration of Short Circuit Event before Failure
the maximum temperature from 110°C to 100°C, with an example of six months
instead of three months (SAR 26259).
The tables in the
clarifying I
Tables for 3.3 V LVCMOS and 1.2 V LVCMOS wide range were added (SAR
79370,
Notes in the wide range tables state that the minimum drive strength for any
LVCMOS 3.3 V (or LVCMOS 1.2 V) software configuration when run in wide
range is ±100 µA. Drive strength displayed in the software is supported for
normal range only. For a detailed I/V curve, refer to the IBIS models (SAR
25700).
The following sentence was deleted from the
5 V–tolerant input buffer and push-pull output buffer (SAR 24916).
The tables in the
Enable Register" section
Characteristics" section
SAR 79353, and SAR 79366
and R
stating the value for PDC4 is the minimum contribution of the PLL when
IL
and I
WEAK PULLDOWN-MAX
"Single-Ended I/O Characteristics" section
IH
"Input Register"
were added.
were updated.
Table 2-16 • Different Components Contributing to the
were updated. The tables in the
R ev isio n 1 1
section,
were revised (SAR 21348).
Changes
).
"Output Register"
was revised to include data for 3.3 V
"2.5 V LVCMOS"
and
was revised, including
was revised to change
Table 2-18 • Different
were updated. Notes
section, and
section: It uses a
WEAK PULL-
"VersaTile
"Output
through
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