LFXP3C-4TN100C Lattice, LFXP3C-4TN100C Datasheet - Page 203

• Manufacturer Part Number: LFXP3C-4TN100C
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 I/O 1.8/2.5/3.3V -4 Spd
• Manufacturer: Lattice

Specifications of LFXP3C-4TN100C

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 9-42. FIFO_DC Without Output Registers, Start of Data Write Cycle
The WrEn signal has to be high to start writing into the FIFO_DC. The Empty and Almost Empty flags are high to
begin and Full and Almost full are low.
When the first data gets written into the FIFO_DC, the Empty flag de-asserts (or goes low), as the FIFO_DC is no
longer empty. In this figure we are assuming that the Almost Empty setting flag setting is 3 (address location 3). So
the Almost Empty flag gets de-asserted when the third address location gets filled.
Now let is assume that we continue to write into the FIFO_DC to fill it. When the FIFO_DC is filled, the Almost Full
and Full Flags are asserted. Figure 9-43 shows the behavior of these flags. In this figure we assume that FIFO_DC
depth is ‘N’.
RPReset
WrClock
RdClock
Almost
Almost
Empty
Empty
Reset
WrEn
RdEn
Data
Full
Full
Q
Invalid Data
Data_1
Data_2
9-38
Invalid Q
Data_3
LatticeECP/EC and LatticeXP Devices
Data_4
Data_5
Memory Usage Guide