LFXP3C-4TN100C Lattice, LFXP3C-4TN100C Datasheet - Page 222

• Manufacturer Part Number: LFXP3C-4TN100C
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 I/O 1.8/2.5/3.3V -4 Spd
• Manufacturer: Lattice

Specifications of LFXP3C-4TN100C

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 10-1. Number of DQS Banks in the LatticeECP/EC Device
Table 10-2. Number of DQS Banks in the LatticeXP Device
100-pin TQFP
144-pin TQFP
208-pin TQFP
256-ball fpBGA
484-ball fpBGA
672-ball fpBGA
1. 10 I/Os (1 DQS + 8 DQs + Bank VREF1) can function as a DDR interface in which the FPGA can have a DM output but not a DQS aligned
100-pin TQFP
144-pin TQFP
208-pin PQFP
256-ball fpBGA
388-ball fpBGA
484-ball fpBGA
672-ball fpBGA
input (in the same DDR bank as the rest of the system).
Package
Package
LFEC1
LFEC3
LFEC1
LFEC3
LFEC6/LFECP6
LFEC1
LFEC3
LFEC6/LFECP6
LFEC10/LFECP10
LFEC3
LFEC6/LFECP6
LFEC10/LFECP10
LFEC15/LFECP15
LFEC6/LFECP6
LFEC10/LFECP10
LFEC15/LFECP15
LFEC20/LFECP20
LFEC33/LFECP33
LFEC20/LFECP20
LFEC33/LFECP33
LFXP3C/LFXP3E
LFXP6C LFXP6E
LFXP3C/LFXP3E
LFXP6C/LFXP6E
LFXP3C/LFXP3E
LFXP6C/LFXP6E
LFXP3C/LFXP3E
LFXP6C/LFXP6E
LFXP10C/LFXP10E
LFXP15C/LFXP15E
LFXP20C/LFXP20E
LFXP10C/LFXP10E
LFXP15C/LFXP15E
LFXP20C/LFXP20E
LFXP15C/LFXP15E
LFXP20C/LFXP20E
LFXP20C/LFXP20E
Device
Device
DQS Groups
DQS Groups
Total x8
Total x8
8+2
8+2
8+2
10
12
12
12
14
18
20
22
22
24
30
12
12
16
16
20
16
20
20
20
20
24
3
3
6
6
6
6
2
2
7
7
8
8
1
1
1
10-3
1+1
1+1
1+1
0
1
1
1
1
1
1
2
2
2
2
2
3
3
3
3
4
4
0
0
0
1
1
1
1
2
2
2
2
3
2
3
3
3
3
4
1
1
1
Number of DQS Groups per I/O Bank
Number of DQS Groups per I/O Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
3
3
3
4
1
0
0
0
0
1
1
2
2
2
2
3
2
3
3
3
3
4
LatticeECP/EC and LatticeXP
2
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
2
2
2
2
3
2
0
0
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
3
0
0
1
1
1
1
1
1
1
1
2
2
2
2
2
2
3
3
3
4
3
0
0
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
4
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
3
3
3
4
4
0
0
1
1
1
1
2
2
2
2
3
2
3
3
3
3
4
DDR Usage Guide
1+1
1+1
1+1
5
0
0
1
1
1
1
2
2
2
2
2
3
3
3
3
4
4
5
1
1
1
1
1
1
2
2
2
2
3
2
3
3
3
3
4
1
1
1
6
0
0
1
1
1
1
1
1
1
1
2
2
2
2
2
2
3
3
3
4
6
0
0
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
7
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
2
2
2
2
3
7
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2