LFEC3E-3QN208C Lattice, LFEC3E-3QN208C Datasheet - Page 68

• Manufacturer Part Number: LFEC3E-3QN208C
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs
• Manufacturer: Lattice

Specifications of LFEC3E-3QN208C

• Number Of Macrocells: 3100
• Number Of Programmable I/os: 145
• Data Ram Size: 56320
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Signal Descriptions (Cont.)
TDI
TDO
V
Configuration Pads (used during sysCONFIG)
CFG[2:0]
INITN
PROGRAMN
DONE
CCLK
BUSY/SISPI
CSN
CS1N
WRITEN
D[7:0]/SPID[0:7]
DOUT/CSON
DI/CSSPIN
CCJ
Signal Name
I/O
I/O
I/O
I/O Configuration Clock for configuring an FPGA in sysCONFIG mode.
I/O Read control command in SPI3 or SPIX mode.
I/O sysCONFIG Port Data I/O.
I/O
—
O
O
I
I
I
I
I
I
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence). Pull-up is enabled during configuration.
Output pin. Test Data out pin used to shift data out of device using 1149.1.
V
Mode pins used to specify configuration modes values latched on rising edge
of INITN. During configuration, a pull-up is enabled. These are dedicated
pins.
Open Drain pin. Indicates the FPGA is ready to be configured. During config-
uration, a pull-up is enabled. It is a dedicated pin.
Initiates configuration sequence when asserted low. This pin always has an
active pull-up. This is a dedicated pin.
Open Drain pin. Indicates that the configuration sequence is complete, and
the startup sequence is in progress. This is a dedicated pin.
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled.
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled.
Write Data on Parallel port (Active low).
Output for serial configuration data (rising edge of CCLK) when using
sysCONFIG port.
Input for serial configuration data (clocked with CCLK) when using sysCON-
FIG port. During configuration, a pull-up is enabled. Output when used in
SPI/SPIX modes.
CCJ
- The power supply pin for JTAG Test Access Port.
4-2
LatticeECP/EC Family Data Sheet
Description
Pinout Information