AGLN125V5-ZVQG100 Actel, AGLN125V5-ZVQG100 Datasheet - Page 43
![FPGA - Field Programmable Gate Array 125K System Gates IGLOO nano](/photos/16/14/161495/tqfp-100_sml.jpg)
AGLN125V5-ZVQG100
Manufacturer Part Number
AGLN125V5-ZVQG100
Description
FPGA - Field Programmable Gate Array 125K System Gates IGLOO nano
Manufacturer
Actel
Datasheet
1.AGLN030V5-ZUCG81.pdf
(140 pages)
Specifications of AGLN125V5-ZVQG100
Processor Series
AGLN125
Core
IP Core
Number Of Macrocells
1024
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
71
Data Ram Size
36 Kbit
Supply Voltage (max)
1.5 V
Supply Current
18 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
125 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGLN125V5-ZVQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AGLN125V5-ZVQG100I
Manufacturer:
Actel
Quantity:
160
Company:
Part Number:
AGLN125V5-ZVQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGLN125V5-ZVQG100I
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Table 2-40 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
3.3 V LVCMOS
Wide Range
Drive
Strength
100 µA
100 µA
100 µA
100 µA
Notes:
1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V Wide Range, as specified in the JEDEC JESD8-B
2. I
3. I
4. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
5. Currents are measured at 85°C junction temperature.
6. Software default selection is highlighted in gray.
specification.
current is larger when operating outside recommended ranges.
equivalent software default drive strength. These values are for normal ranges only.
IL
IH
is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
1
3.3 V LVCMOS Wide Range
Equivalent
Software
Strength
Option
Default
Drive
2 mA
4 mA
6 mA
8 mA
4
Min.
–0.3
–0.3
–0.3
–0.3
V
VIL
Max.
0.8
0.8
0.8
0.8
V
Min.
V
2
2
2
2
VIH
Max.
R ev i si o n 1 1
3.6
3.6
3.6
3.6
V
Max.
VOL
0.2
0.2
0.2
0.2
V
VCCI – 0.2 100
VCCI – 0.2 100
VCCI – 0.2 100
VCCI – 0.2 100
VOH
Min.
V
IGLOO nano Low Power Flash FPGAs
I
µA
OL
100
100
100
100
I
µA
OH
µA
I
10
10
10
10
IL
2
5
I
µA
IH
10
10
10
10
2- 29
3
5