AGLN125V5-ZVQG100 Actel, AGLN125V5-ZVQG100 Datasheet - Page 99
![FPGA - Field Programmable Gate Array 125K System Gates IGLOO nano](/photos/16/14/161495/tqfp-100_sml.jpg)
AGLN125V5-ZVQG100
Manufacturer Part Number
AGLN125V5-ZVQG100
Description
FPGA - Field Programmable Gate Array 125K System Gates IGLOO nano
Manufacturer
Actel
Datasheet
1.AGLN030V5-ZUCG81.pdf
(140 pages)
Specifications of AGLN125V5-ZVQG100
Processor Series
AGLN125
Core
IP Core
Number Of Macrocells
1024
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
71
Data Ram Size
36 Kbit
Supply Voltage (max)
1.5 V
Supply Current
18 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
125 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGLN125V5-ZVQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AGLN125V5-ZVQG100I
Manufacturer:
Actel
Quantity:
160
Company:
Part Number:
AGLN125V5-ZVQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGLN125V5-ZVQG100I
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Table 2-108 • FIFO
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
ENS
ENH
BKS
BKH
DS
DH
CKQ1
CKQ2
RCKEF
WCKFF
CKAF
RSTFG
RSTAF
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
For specific junction temperature and voltage supply levels, refer to
1.2 V DC Core Voltage
Worst Commercial-Case Conditions: T
REN_B, WEN_B Setup Time
REN_B, WEN_B Hold Time
BLK_B Setup Time
BLK_B Hold Time
Input Data (DI) Setup Time
Input Data (DI) Hold Time
Clock HIGH to New Data Valid on DO (flow-through)
Clock HIGH to New Data Valid on DO (pipelined)
RCLK HIGH to Empty Flag Valid
WCLK HIGH to Full Flag Valid
Clock HIGH to Almost Empty/Full Flag Valid
RESET_B LOW to Empty/Full Flag Valid
RESET_B LOW to Almost Empty/Full Flag Valid
RESET_B LOW to Data Out LOW on DO (flow-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
RESET_B Recovery
RESET_B Minimum Pulse Width
Clock Cycle Time
Maximum Frequency for FIFO
Description
J
= 70°C, VCC = 1.14 V
R ev i si o n 1 1
Table 2-7 on page 2-7
IGLOO nano Low Power Flash FPGAs
for derating values.
22.17
21.94
10.90
3.44
0.26
0.30
0.00
1.30
0.41
5.67
3.02
6.02
5.71
5.93
3.41
4.09
1.02
5.48
1.18
Std.
92
Units
3.41
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 85