LFE2M35SE-5FN484C Lattice, LFE2M35SE-5FN484C Datasheet - Page 115
![FPGA - Field Programmable Gate Array 34K LUTs S-Ser SERDE S Mem DSP 1.2V -5](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M35SE-5FN484C
Manufacturer Part Number
LFE2M35SE-5FN484C
Description
FPGA - Field Programmable Gate Array 34K LUTs S-Ser SERDE S Mem DSP 1.2V -5
Manufacturer
Lattice
Datasheet
1.LFE2M35SE-5FN484C.pdf
(389 pages)
Specifications of LFE2M35SE-5FN484C
Number Of Macrocells
34000
Maximum Operating Frequency
320 MHz
Number Of Programmable I/os
303
Data Ram Size
2151424
Delay Time
12 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M35SE-5FN484C
Manufacturer:
LATTICE
Quantity:
210
Company:
Part Number:
LFE2M35SE-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LFE2M35SE-5FN484C
Manufacturer:
LATTICE
Quantity:
20 000
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LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 (Cont.)
Lattice Semiconductor
Available DDR-Interfaces per
I/O Bank
PCI Capable I/Os per Bank
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1
DQSB + 8 DQs + 1 DM + Bank VREF1).
1
Pin Type
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
256 fpBGA 484 fpBGA 256 fpBGA 484 fpBGA 672 fpBGA
4-12
32
20
16
28
0
0
0
0
2
1
0
1
0
0
0
0
0
0
LFE2M20
62
28
40
40
0
0
1
1
4
2
3
2
0
0
0
0
0
0
LatticeECP2/M Family Data Sheet
32
20
16
28
0
0
0
0
2
1
0
1
0
0
0
0
0
0
Pinout Information
LFE2M35
62
28
39
40
0
0
1
1
4
2
1
2
0
0
0
0
0
0
50
60
52
60
0
0
3
2
3
3
2
3
0
0
0
0
0
0
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