LFE2M35SE-5FN484C Lattice, LFE2M35SE-5FN484C Datasheet - Page 19
![FPGA - Field Programmable Gate Array 34K LUTs S-Ser SERDE S Mem DSP 1.2V -5](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M35SE-5FN484C
Manufacturer Part Number
LFE2M35SE-5FN484C
Description
FPGA - Field Programmable Gate Array 34K LUTs S-Ser SERDE S Mem DSP 1.2V -5
Manufacturer
Lattice
Datasheet
1.LFE2M35SE-5FN484C.pdf
(389 pages)
Specifications of LFE2M35SE-5FN484C
Number Of Macrocells
34000
Maximum Operating Frequency
320 MHz
Number Of Programmable I/os
303
Data Ram Size
2151424
Delay Time
12 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Company:
Part Number:
LFE2M35SE-5FN484C
Manufacturer:
LATTICE
Quantity:
210
Company:
Part Number:
LFE2M35SE-5FN484C
Manufacturer:
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Quantity:
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Part Number:
LFE2M35SE-5FN484C
Manufacturer:
LATTICE
Quantity:
20 000
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Lattice Semiconductor
this special vertical routing channel and the eight secondary clock regions for the ECP2-50. LatticeECP2 devices
have four secondary clocks (SC0 to SC3) which are distrubed to every region.
The secondary clock muxes are located in the center of the device. Figure 2-16 shows the mux structure of the
secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for
high fan-out signals.
Figure 2-15. Secondary Clock Regions ECP2-50
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
I/O Bank 0
I/O Bank 5
Region 1
Region 2
Region 3
Region 4
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
2-16
I/O Bank 1
I/O Bank 4
Region 5
Region 6
Region 7
Region 8
LatticeECP2/M Family Data Sheet
Vertical Routing
Channel Regional
Boundary
DSP Row
Regional
Boundary
DSP Row
Regional
Boundary
EBR Row
Regional
Boundary
Architecture
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