LFE2M35SE-5FN484C Lattice, LFE2M35SE-5FN484C Datasheet - Page 39
![FPGA - Field Programmable Gate Array 34K LUTs S-Ser SERDE S Mem DSP 1.2V -5](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M35SE-5FN484C
Manufacturer Part Number
LFE2M35SE-5FN484C
Description
FPGA - Field Programmable Gate Array 34K LUTs S-Ser SERDE S Mem DSP 1.2V -5
Manufacturer
Lattice
Datasheet
1.LFE2M35SE-5FN484C.pdf
(389 pages)
Specifications of LFE2M35SE-5FN484C
Number Of Macrocells
34000
Maximum Operating Frequency
320 MHz
Number Of Programmable I/os
303
Data Ram Size
2151424
Delay Time
12 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Lattice Semiconductor
Top Edge
The PICs on the top edge are different from PIOs on the left, right and bottom edges. PIOs on this edge do not
have DDR registers or DQS signals.
The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi-
tional detail is provided in the Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR
data from the memory into input register blocks. Interfaces on the left and right edges are designed for DDR mem-
ories that support 16 bits of data, whereas interfaces on the bottom are designed for memories that support 18 bits
of data.
Figure 2-33. DQS Input Routing for the Left and Right Edges of the Device
DQS
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
2-36
sysIO
Buffer
Delay
LatticeECP2/M Family Data Sheet
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADB "C"
PADB "C"
PADA "T"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
DQS Pin
PADA "T"
PADB "C"
Assigned
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
Architecture
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