AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 92

• Manufacturer Part Number: AFS600-FGG256
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-FGG256

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 119
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
FIFO Flag Usage Considerations
The AEVAL and AFVAL pins are used to specify the 12-bit AEMPTY and AFULL threshold values,
respectively. The FIFO contains separate 12-bit write address (WADDR) and read address (RADDR)
counters. WADDR is incremented every time a write operation is performed, and RADDR is incremented
every time a read operation is performed. Whenever the difference between WADDR and RADDR is
greater than or equal to AFVAL, the AFULL output is asserted. Likewise, whenever the difference
between WADDR and RADDR is less than or equal to AEVAL, the AEMPTY output is asserted. To
handle different read and write aspect ratios, AFVAL and AEVAL are expressed in terms of total data bits
instead of total data words. When users specify AFVAL and AEVAL in terms of read or write words, the
SmartGen tool translates them into bit addresses and configures these signals automatically. SmartGen
configures the AFULL flag to assert when the write address exceeds the read address by at least a
predefined value. In a 2k×8 FIFO, for example, a value of 1,500 for AFVAL means that the AFULL flag
will be asserted after a write when the difference between the write address and the read address
reaches 1,500 (there have been at least 1500 more writes than reads). It will stay asserted until the
difference between the write and read addresses drops below 1,500.
The AEMPTY flag is asserted when the difference between the write address and the read address is
less than a predefined value. In the example above, a value of 200 for AEVAL means that the AEMPTY
flag will be asserted when a read causes the difference between the write address and the read address
to drop to 200. It will stay asserted until that difference rises above 200. Note that the FIFO can be
configured with different read and write widths; in this case, the AFVAL setting is based on the number of
write data entries and the AEVAL setting is based on the number of read data entries. For aspect ratios
of 512×9 and 256×18, only 4,096 bits can be addressed by the 12 bits of AFVAL and AEVAL. The
number of words must be multiplied by 8 and 16, instead of 9 and 18. The SmartGen tool automatically
uses the proper values. To avoid halfwords being written or read, which could happen if different read
and write aspect ratios are specified, the FIFO will assert FULL or EMPTY as soon as at least a minimum
of one word cannot be written or read. For example, if a two-bit word is written and a four-bit word is
being read, the FIFO will remain in the empty state when the first word is written. This occurs even if the
FIFO is not completely empty, because in this case, a complete word cannot be read. The same is
applicable in the full state. If a four-bit word is written and a two-bit word is read, the FIFO is full and one
word is read. The FULL flag will remain asserted because a complete word cannot be written at this
point.
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