LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 211

• Manufacturer Part Number: LFXP3C-3TN144I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
• Manufacturer: Lattice

Specifications of LFXP3C-3TN144I

• Number Of Programmable I/os: 100
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-144
• Package: 144TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 100
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 9-54. PFU Based Distributed Single Port RAM Timing Waveform – with Output Registers
Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based
PFU-based Distributed Dual Port RAM is also created using the four input LUT (Look-Up Table) available in the
PFU. These LUTs can be cascaded to create larger distributed memory sizes.
Figure 9-55 shows the Distributed Single Port RAM module as generated by IPexpress.
Figure 9-55. Distributed Dual Port RAM Module Generated by IPexpress
The generated module makes use of a 4-input LUT available in the PFU. Additional logic for Clocks, Clock Enables
and Reset is generated by utilizing the resources available in the PFU. The basic Distributed Dual Port RAM primi-
tive for the LatticeECP/EC and LatticeXP devices is shown in Figure 9-56.
ClockEn
Address
Reset
Clock
Data
WE
Q
t
t
SUWREN_PFU
SUADDR_PFU
t
SUDATA_PFU
Data_0
Add_0
RdClockEn
WrClockEn
WrAddress
RdAddress
t
t
HADDR_PFU
HDATA_PFU
RdClock
WrClock
Invalid Data
Reset
Data
WE
Data_1
Add_1
t
HWREN_PFU
Distributed Dual Port
9-46
PFU based
Memory
Add_0
LatticeECP/EC and LatticeXP Devices
t
CO?
Data_0
Add_1
Q
Memory Usage Guide
Data_1
Add_2
Data_2