LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 319

• Manufacturer Part Number: LFXP3C-3TN144I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
• Manufacturer: Lattice

Specifications of LFXP3C-3TN144I

• Number Of Programmable I/os: 100
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-144
• Package: 144TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 100
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

February 2006
Introduction
This document describes the functionality and usage of ispTRACY™, Lattice’s integrated logic analyzer for the
ispXPGA
TRACY tool consists of an Intellectual Property (IP) hardware block and three software tools – Core Generator,
Core Linker and ispLA. ispTRACY allows for fast debugging and functional verification inside Lattice FPGA devices
without the need for expensive test and measurement equipment. Debugging is accomplished through the hard-
ware IP compiled in the design, on device block RAM and the device JTAG port.
ispTRACY IP Core Features
The ispTRACY IP core is highly configurable. These configurable features include width and depth of data capture
lines, multiple edge and level sensitive trigger signals, complex comparison for trigger events, delayed trigger
events and more. ispTRACY allows multiple ispTRACY IP cores to be included in a single design. The following
table summarizes the features of the ispTRACY IP core.
Table 14-1. ispTRACY IP Core Features
ispTRACY IP Module Generator
To include ispTRACY cores in a design, the first step is to run IPexpress™ from the ispLEVER
Figure 14-1 shows the launch button for the IP Manager program.
Figure 14-1. IPexpress Launch Button in ispLEVER Project Navigator
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
Depth of Memory Capture
Data Capture Width
Triggering Schemes
Number of Triggers
Number of Core
®
, LatticeSC™, LatticeECP2™, LatticeECP™, LatticeEC™ and LatticeXP™ FPGA families. The isp-
Feature
256 to 4096 samples
8 to 256 bits
Rising/falling edges, level logic, comparison, trigger after combination of events
4 to 128 bits, can be a combination of edge and level sensitive signals
Up to 16 ispTRACY cores
14-1
Description
Lattice ispTRACY
Usage Guide
Technical Note TN1054
®
Project Navigator.
tn1054_01.2