A40MX02-PLG68 Actel, A40MX02-PLG68 Datasheet - Page 18

• Manufacturer Part Number: A40MX02-PLG68
• Description: FPGA - Field Programmable Gate Array 3K System Gates
• Manufacturer: Actel

Specifications of A40MX02-PLG68

• Processor Series: A40MX02
• Core: IP Core
• Number Of Macrocells: 295
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 57
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 3000
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

JTAG Mode Activation
The JTAG test logic circuit is activated in the Designer
software by selecting Tools -> Device Selection. This
brings up the Device Selection dialog box as shown in
Figure
clicking the "Reserve JTAG Pins" check box.
explains the pins' behavior in either mode.
Table 5 •
TRST Pin and TAP Controller Reset
An active reset (TRST) pin is not supported; however, MX
devices contain power-on circuitry that resets the
boundary scan circuitry upon power-up. Also, the TMS
pin is equipped with an internal pull-up resistor. This
allows the TAP controller to remain in or return to the
Test-Logic-Reset state when there is no input or when a
logical 1 is on the TMS pin. To reset the controller, TMS
must be HIGH for at least five TCK cycles.
1 -1 2
Reserve JTAG
TCK
TDI, TMS
TDO
40MX and 42MX FPGA Families
1-15. The JTAG test logic circuit can be enabled by
Boundary Scan Pin Configuration and Functionality
BST input; must be terminated to logical HIGH or LOW to avoid floating
BST input; may float or be tied to HIGH
BST output; may float or be connected to TDI of another device
Table 5
Checked
v6.1
Figure 1-15 • Device Selection Wizard
Boundary Scan Description Language
(BSDL) File
Conforming to the IEEE Standard 1149.1 requires that
the operation of the various JTAG components be
documented. The BSDL file provides the standard format
to describe the JTAG components that can be used by
automatic test equipment software. The file includes the
instructions that are supported, instruction bit pattern,
and the boundary-scan chain order. For an in-depth
discussion on BSDL files, please refer to
Format Description
Actel BSDL files are grouped into two categories -
generic and device-specific. The generic files assign all
user I/Os as inouts. Device-specific files assign user I/Os as
inputs, outputs or inouts.
Generic files for MX devices are available on Actel's website
at http://www.actel.com/techdocs/models/bsdl.html.
application note.
Unchecked
User I/O
User I/O
User I/O
Actel BSDL Files