A40MX02-PLG68 Actel, A40MX02-PLG68 Datasheet - Page 55

• Manufacturer Part Number: A40MX02-PLG68
• Description: FPGA - Field Programmable Gate Array 3K System Gates
• Manufacturer: Actel

Specifications of A40MX02-PLG68

• Processor Series: A40MX02
• Core: IP Core
• Number Of Macrocells: 295
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 57
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 3000
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 32 •
Parameter Description
Input Module Propagation Delays
t
t
t
t
Input Module Predicted Routing Delays
t
t
t
t
t
Global Clock Network
t
t
t
t
t
t
t
t
f
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
5. Delays based on 35 pF loading.
INYH
INYL
INGH
INGL
IRD1
IRD2
IRD3
IRD4
IRD8
CKH
CKL
PWH
PWL
CKSW
SUEXT
HEXT
P
MAX
device performance. Post-route timing analysis or simulation is required to determine actual performance.
obtained from the Timer utility.
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, V
Pad-to-Y HIGH
Pad-to-Y LOW
G to Y HIGH
G to Y LOW
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Input LOW to HIGH
Input HIGH to LOW
Minimum Pulse
Width HIGH
Minimum Pulse
Width LOW
Maximum Skew
Input Latch External
Set-Up
Input Latch External
Hold
Minimum Period
Maximum Frequency FO = 32
PD1
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 256
+ t
RD1
+ t
2
PDn
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
‘–3’ Speed
1.2
1.3
1.2
1.3
0.0
0.0
2.3
2.2
3.4
3.7
, t
CO
CCA
+ t
296
268
1.0
0.8
1.3
1.3
2.0
2.3
2.5
2.8
3.7
2.4
2.7
3.5
3.9
0.3
0.3
RD1
= 4.75V, T
+ t
v6.1
‘–2’ Speed
PDn
1.4
1.5
1.4
1.5
0.0
0.0
2.6
2.4
3.7
4.1
, or t
J
= 70°C)
269
244
PD1
1.2
0.9
1.4
1.4
2.2
2.5
2.8
3.1
4.1
2.7
3.0
3.9
4.3
0.3
0.3
+ t
RD1
‘–1’ Speed
1.5
1.7
1.5
1.7
0.0
0.0
3.0
3.3
4.0
4.5
+ t
SUD
247
224
1.3
1.0
1.6
1.6
2.5
2.9
3.2
3.5
4.7
3.0
3.4
4.4
4.9
0.4
0.4
, whichever is appropriate.
‘Std’ Speed
1.8
2.0
1.8
2.0
0.0
0.0
3.5
3.9
4.7
5.2
40MX and 42MX FPGA Families
215
195
1.6
1.2
1.9
1.9
3.0
3.4
3.7
4.1
5.5
3.6
4.0
5.2
5.7
0.5
0.5
‘–F’ Speed
2.5
2.7
2.5
2.7
0.0
0.0
4.9
5.5
7.8
8.6
129
117
2.2
1.7
2.7
2.7
4.2
4.7
5.2
5.7
7.7
5.0
5.5
7.3
8.0
0.6
0.6
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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