LFX125EB-04FN256C Lattice, LFX125EB-04FN256C Datasheet - Page 21

• Manufacturer Part Number: LFX125EB-04FN256C
• Description: FPGA - Field Programmable Gate Array E-Ser139K Gt ispJTAG 2.5/3.3V -4 Spd
• Manufacturer: Lattice

Specifications of LFX125EB-04FN256C

• Number Of Macrocells: 1936
• Number Of Programmable I/os: 160
• Data Ram Size: 94208
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.65 V
• Number Of Gates: 139 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Absolute Maximum Ratings
Supply Voltage (V
PLL Supply Voltage (V
Output Supply Voltage (V
IEEE 1149.1 TAP Supply Voltage (V
Input Voltage Applied
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C. . . . . . . . . -65 to 150°C
Junction Temperature (T
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and undershoot of -2V to (V
5. A maximum of 64 I/Os per device with V
Recommended Operating Conditions
E
Hot Socketing Characteristics
V
V
V
T
T
1. sysHSI specification is valid for V
I
1. Insensitive to sequence of V
2. LVTTL, LVCMOS only.
3. 0 < V
4. I
Symbol
Erase/Reprogram Cycle
1. Valid over commercial temperature range.
DK
J
J
CC
CCP
CCJ
2
operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, following the programming specifications).
CMOS Erase Reprogram Specifications
rise/fall rates for V
(COM)
(IND)
DK
Symbol
is additive to I
CC
Input or Tristated I/O Leakage Current 0 ≤ V
≤ V
CC
(MAX), 0 < V
Supply Voltage for 1.8V device
Supply Voltage for 2.5V device
Supply Voltage for 3.3V device
Supply Voltage for PLL and sysHSI blocks, 1.8V devices
Supply Voltage for PLL and sysHSI blocks, 2.5V devices
Supply Voltage for PLL and sysHSI blocks, 3.3V devices
Supply Voltage for IEEE 1149.1 Test Access Port for LVCMOS 1.8V
Supply Voltage for IEEE 1149.1 Test Access Port for LVCMOS 2.5V
Supply Voltage for IEEE 1149.1 Test Access Port for LVCMOS 3.3V
Junction Temperature Commercial Operation
Junction Temperature Industrial Operation
PU
CC
CC
, I
and V
) . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V
PD
4, 5
Parameter
CCP
1
or I
. . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V . . . . . . . . . .-0.5 to 5.5V
J
CCO
CCO
) with Power Applied . . -55 to 150°C. . . . . . . . . -55 to 150°C
CCO
CC
BH
) . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V
. Device defaults to pull-up until non-volatile cells are active.
, provided (V
and V
) . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V
≤ V
CC
CCO
and V
CCO
(MAX).
CCJ
CCP
when V
IH
Parameter
IN
IN
) . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V
(MAX) + 2) volts not to exceed 6V is permitted for a duration of <20ns.
- V
> 3.6V is allowed.
= 1.7V to 1.9V.
1, 2, 3
CCO
CCO
1
1, 2, 3, 4
Parameter
) ≤ 3.6V.
≤ 1.0V. For V
IN
≤ 3.0V
1.8V
21
Condition
CCO
> 1.0V, V
1
CC
min must be present. However, assumes monotonic
2.5V/3.3V
ispXPGA Family Data Sheet
Min
—
1,000
1.65
1.65
1.65
Min
Min
-40
2.3
3.0
2.3
3.0
2.3
3.0
0
+/-50
Typ
Max
Max
1.95
1.95
1.95
105
+/-800
2.7
3.6
2.7
3.6
2.7
3.6
85
—
Max
Cycles
Units
Units
Units
C
C
V
V
V
V
V
V
V
V
V
μA