LFX125EB-04FN256C Lattice, LFX125EB-04FN256C Datasheet - Page 61
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LFX125EB-04FN256C
Manufacturer Part Number
LFX125EB-04FN256C
Description
FPGA - Field Programmable Gate Array E-Ser139K Gt ispJTAG 2.5/3.3V -4 Spd
Manufacturer
Lattice
Specifications of LFX125EB-04FN256C
Number Of Macrocells
1936
Number Of Programmable I/os
160
Data Ram Size
94208
Supply Voltage (max)
3.6 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.65 V
Number Of Gates
139 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFX125EB-04FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Signal Descriptions
HSImA_CDRRST, HSImB_CDRRST
HSIm_CSLOCK, HSIm_CSLOCK
sysHSI Block (Source Synchronous Mode)
SS_CLKIN0P, SS_CLKIN1P
SS_CLKIN0N, SS_CLKIN1N
SS_CLKOUT0P, SS_CLKOUT1P
SS_CLKOUT0N, SS_CLKOUT1N
CAL0, CAL1
1. x is a variable for the I/O number.
2. y is a variable for the I/O Bank.
3. z is a variable for the PLL number.
4. m is a variable for the sysHSI block number.
5. A and B refer to the sysHSI block channels.
6. 0 and 1 refer to Source Synchronous group 0 and 1
7. n is a variable for the GCLK and Input number
8. See Logic Signal Connections Table for differential pairing.
Signal Name
1
(Cont.)
Internal Signal Indicates when the CSPLL circuit is locked
Signal Type
6
Output
Output
Input
Input
Input
Input
CDR Reset
P-side of differential clock input
N-side of differential clock input
P-side of differential clock output
N-side of differential clock output
Initiates source synchronous calibration sequence
61
Description
ispXPGA Family Data Sheet
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