LFX125EB-04FN256C Lattice, LFX125EB-04FN256C Datasheet - Page 41

• Manufacturer Part Number: LFX125EB-04FN256C
• Description: FPGA - Field Programmable Gate Array E-Ser139K Gt ispJTAG 2.5/3.3V -4 Spd
• Manufacturer: Lattice

Specifications of LFX125EB-04FN256C

• Number Of Macrocells: 1936
• Number Of Programmable I/os: 160
• Data Ram Size: 94208
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.65 V
• Number Of Gates: 139 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispXPGA 500B/C & ispXPGA 500EB/EC PIC Timing Parameters
ispXPGA 500B/C & ispXPGA 500EB/EC PFU Timing Parameters (Cont.)
Reset/Set
t
t
t
t
t
1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices.
2. t
Register/Latch Delays
t
t
t
t
t
t
t
t
t
t
t
t
Input/Output Delays
t
t
t
t
t
1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices.
IO_CO
IO_S
IO_H
IOCE_S
IOCE_H
IO_GO
IOL_S
IOL_H
IOLPD
IOASRO
IOASRPW
IOASRR
IOBUF
IOIN
IOEN
IODIS
IOFT
LASSRO
LASSRPW
LASSRR
LSSR_S
LSSR_H
Parameter
Parameter
LCTHRUL
quoted bit by bit.
Asynchronous Set/Reset to Output
Asynchronous Set/Reset Pulse Width
Asynchronous Set/Reset Recovery
Synchronous Set/Reset Setup Time
Synchronous Set/Reset Hold Time
Register Clock to Output Delay
Register Setup Time (Data before Clock)
Register Hold Time (Data after Clock)
Register Clock Enable Setup Time
Register Clock Enable Hold Time
Latch Gate to Output Delay
Latch Setup Time
Latch Hold Time
Latch Propagation Delay (Transparent Mode)
Asynchronous Set/Reset to Output
Asynchronous Set/Reset Pulse Width
Asynchronous Set/Reset Recovery Time
Output Buffer Delay
Input Buffer Delay
Output Enable Delay
Output Disable Delay
Feed-thru Delay
Description
Description
Over Recommended Operating Conditions
41
-0.03
-0.03
Min.
Min.
4.19
0.03
0.05
0.06
0.13
0.05
0.06
4.19
—
—
—
—
—
—
—
—
—
—
—
—
-5
-5
1
1
Max.
Max.
-0.12
0.52
0.19
1.09
0.51
1.00
0.78
0.09
1.11
0.23
0.98
0.65
—
—
—
—
—
—
—
—
—
ispXPGA Family Data Sheet
-0.03
-0.03
Min.
4.50
0.03
Min.
0.05
0.06
0.13
0.05
0.06
4.50
—
—
—
—
—
—
—
—
—
—
—
—
-4
-4
-0.11
Max.
Max.
1.17
0.55
1.07
0.84
0.10
1.19
0.25
1.05
0.70
0.56
0.20
—
—
—
—
—
—
—
—
—
—
-0.03
-0.03
Min.
5.18
0.03
Min.
0.06
0.07
0.15
0.06
0.07
5.18
—
—
—
—
—
—
—
—
—
—
—
—
-3
-3
-0.09
Max.
Max.
1.35
0.63
1.23
0.97
0.12
1.37
0.29
1.21
0.81
0.64
0.23
—
—
—
—
—
—
—
—
—
—
Timing v.0.3
Timing v.0.3
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns