AD9553BCPZ Analog Devices Inc, AD9553BCPZ Datasheet - Page 39

IC INTEGER-N CLCK GEN 32LFCSP

AD9553BCPZ

Manufacturer Part Number
AD9553BCPZ
Description
IC INTEGER-N CLCK GEN 32LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9553BCPZ

Clock Ic Type
PLL Clock Driver
Ic Interface Type
3 Wire, Serial
Frequency
710MHz
No. Of Outputs
2
Supply Current
162mA
Supply Voltage Range
0V To 3.3V
Digital Ic Case Style
LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
AD9553BCPZ
Manufacturer:
ADI
Quantity:
154
REFB Frequency Control (Register 0x23 to Register 0x26)
Table 35.
Address
0x23
0x24
0x25
0x26
DCXO Frequency and Reference Switchover Control (Register 0x27 to Register 0x31)
Table 36.
Address
0x27
0x28
0x29
0x2A to
0x31
Bit
[7:0]
[7:2]
1
0
7
6
5
4
[3:0]
[7:0]
Bit
[7:0]
[7:2]
1
0
[7:6]
5
[4:0]
[7:0]
Bit Name
REFB divider (R
REFB divider (R
Enable SPI control of R
Unused
Enable SPI control of ×2
Select ×2
Enable SPI control of ÷5
Select ÷5
Unused
Unused
Bit Name
XO divider (R
XO divider (R
Enable SPI control of R
Unused
Switchover mode
REFA diff
Unused
Unused
B
B
XO
XO
)
)
B
B
)
)
B
XO
B
B
Description
Bits[13:6] of the 14-bit REFB divider.
Bits[5:0] of the 14-bit REFB divider (default: R
are ineffective unless Register 0x24[1] = 1.
Enables SPI port control of the REFB divider value (R
0 = the A3 to A0 pins define R
1 = the 14-bit value in the REFB divider register defines R
Unused.
Enables SPI control of the REFB ×2 frequency multiplier (×2
0 = the device automatically selects ×2
1 = Register 0x25[6] controls the selection of ×2
Selects ×2
0 = bypass ×2
1 = select ×2
Enables SPI control of the ÷5
0 = the device automatically selects ÷5
1 = Register 0x25[4] controls the selection of ÷5
Selects ÷5
0 = bypass ÷5
1 = select ÷5
Unused.
Unused.
Description
Bits[13:6] of the 14-bit XO divider.
Bits[5:0] of the 14-bit XO divider (default: R
ineffective unless Register 0x28[1] = 1.
Enables SPI port control of the XO divider value (R
0 = the A3 to A0 pins define R
1 = the 14-bit value in the XO divider register defines R
Unused.
Selects the switchover operating mode.
00 = revertive switchover (default).
01 = nonrevertive switchover.
10 = selects REFA as the active reference.
11 = selects REFB as the active reference.
Enables the differential input reference function.
0 = normal single-ended operation of REFA and REFB (default).
1 = REFA configured as a differential reference in which the REFA pin functions as one
differential input and the REFB/REFA pin functions as the other differential input. In this
configuration, the REFB channel and switchover functionality are both unavailable.
Unused.
Unused.
Rev. A | Page 39 of 44
B
B
. This bit is ineffective unless Register 0x25[7] = 1.
. This bit is ineffective unless Register 0x25[5] = 1.
B
B
.
.
B
B
(default).
(default).
B
B
XO
prescaler per Register 0x25[4].
per Table 14 (default).
per Table 14 (default).
B
B
per Table 14 (default).
per Table 14 (default).
XO
B
= 4096 decimal). The XO divider bits are
= 8192 decimal). The REFB divider bits
B
B
.
.
XO
).
B
).
XO
.
B
.
B
) per Register 0x25[6].
AD9553

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