AD9553BCPZ Analog Devices Inc, AD9553BCPZ Datasheet - Page 41

• Manufacturer Part Number: AD9553BCPZ
• Description: IC INTEGER-N CLCK GEN 32LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9553BCPZ

• Clock Ic Type: PLL Clock Driver
• Ic Interface Type: 3 Wire, Serial
• Frequency: 710MHz
• No. Of Outputs: 2
• Supply Current: 162mA
• Supply Voltage Range: 0V To 3.3V
• Digital Ic Case Style: LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OUT2 Driver Control (Register 0x34)
Table 39.
Address
0x34
Bit
7
6
[5:3]
2
1
0
Bit Name
OUT2 drive strength
OUT2 power-down
OUT2 mode control
OUT2 CMOS polarity
Unused
OUT1 mode source
Description
Controls the output drive capability of the OUT2 driver.
0 = weak.
1 = strong (default).
Controls power-down functionality of the OUT2 driver.
0 = OUT2 active (default).
1 = OUT2 powered down.
OUT2 driver mode selection.
000 = CMOS, both pins active.
001 = CMOS, positive pin active, negative pin tristate.
010 = CMOS, positive pin tristate, negative pin active.
011 = CMOS, both pins tristate.
100 = LVDS.
101 = LVPECL (default).
110 = not used.
111 = not used.
Selects the polarity of the OUT2 pins in CMOS mode. This bit is ineffective unless Bits[5:3]
select CMOS mode. See the Output Driver Polarity (CMOS) section for the definition of
normal and inverted polarity.
0 = positive pin is normal polarity and negative pin is normal polarity (default).
1 = positive pin logic is inverted polarity and negative pin is normal polarity.
Unused.
Controls OUT2 driver functionality (see Figure 31).
0 = OUT2 mode determined by the OM2 to OM0 pins (default).
1 = OUT2 mode defined by Register 0x34[5:3].
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AD9553