SI5321-H-BL Silicon Laboratories Inc, SI5321-H-BL Datasheet - Page 18

• Manufacturer Part Number: SI5321-H-BL
• Description: IC CLOCK MULT SONET/SDH 63-PBGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5321-H-BL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BWBOOST
Si5321
The Si5321 clock input frequencies are variable within
the range specified in Table 3 on page 7. The output
rates are scaled accordingly. If a 19.44 MHz input clock
is used, the clock output frequency is 19.44, 38.88,
77.76, 155.52 MHz, etc.
18
Table 7. Loop Bandwidth and FEC Settings
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
External Inputs
BWSEL
[1:0]
00
00
00
00
00
00
00
00
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
00
10
11
01
01
01
01
01
01
01
01
01
[2:0]
FEC
000
001
010
011
100
101
110
000
001
010
011
100
101
110
000
001
010
011
100
101
110
0xx
0xx
0xx
0xx
000
001
010
011
100
101
110
111
111
111
111
Conversion
Reserved
Reserved
Reserved
Reserved
Effective
255/238
238/255
255/237
237/255
255/238
238/255
255/237
237/255
255/238
238/255
255/237
237/255
255/238
238/255
255/237
237/255
66/64
64/66
66/64
64/66
66/64
64/66
66/64
64/66
Rate
FEC
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Bandwidth
Effective
12800
3200
3200
3200
3200
3200
3200
3200
6400
6400
6400
6400
6400
6400
6400
6400
1600
3200
1600
1600
1600
1600
1600
1600
1600
PLL
(Hz)
800
800
800
800
800
800
800
—
—
—
—
Rev. 2.5
2.2.1. FEC Rate Conversion
The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x,
1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock frequency
multiplication function with an option for additional
forward or reverse frequency scaling by a factor of 255/
238 (15/14), 255/237 (85/79), or 66/64 (33/32) for FEC
rate conversion applications. The 255/237 and the 66/
64 rate conversions requires the input clock rate to be in
the 155 MHz or higher ranges. The multiplication factor
is configured by selecting the input and output clock
frequency ranges for the device. The additional
frequency scaling for FEC rate conversion is selected
using the FEC[2:0] control inputs.
For example, a 622.08 MHz output clock (a non-FEC
rate) can be generated from a 19.44 MHz input clock (a
non-FEC
(19.44 MHz range), setting FRQSEL[2:0] = 011 (32x
multiplication) and setting FEC[2:0] = 000 (no FEC
scaling). A 666.51 MHz output clock (an FEC rate) can
be generated from a 19.44 MHz input clock (a non-FEC
rate) by setting INFRQSEL[2:0] = 001 (19.44 MHz
range), setting FRQSEL[2:0] = 011 (32x multiplication)
Output Clock
Frequency
Range
2,488.32 MHz
1244.16 MHz
622.08 MHz
311.04 MHz
155.52 MHz
77.76 MHz
38.88 MHz
19.44 MHz
Input Clock
Frequency
Range
Reserved
622 MHz
311 MHz
155 MHz
77 MHz
38 MHz
19 MHz
Reserved
Table 9. Nominal Clock Output Frequencies
Table 8. Nominal Clock Input Frequencies
rate)
INFRQSEL2 INFRQSEL1 INFRQSEL0
FRQSEL2
by
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
0
setting
FRQSEL1
INFRQSEL[2:0] = 001
1
1
0
0
1
1
0
0
1
1
1
0
1
0
0
0
FRQSEL0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
1