SI5321-H-BL Silicon Laboratories Inc, SI5321-H-BL Datasheet - Page 29

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SI5321-H-BL

Manufacturer Part Number
SI5321-H-BL
Description
IC CLOCK MULT SONET/SDH 63-PBGA
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI5321-H-BL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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*Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a
A4–8, B5, B8
D6, D7, E6,
C3–C7, E2,
F2, G2–G8
B6, B7, C8
E7, F3–F7
Pin #
H2
logic low state if the input is not driven from an external source.
RSVD_GND
RSVD_NC
Pin Name
V
REXT
GND
DD25
Table 10. Si5321 Pin Descriptions (Continued)
GND
V
I/O
DD
I
Signal Level
Analog
Supply
Supply
LVTTL
LVTTL
Rev. 2.5
2.5 V Compensation Network.
These pins provide a means of connecting the
compensation network for the on-chip regulator.
Ground.
Must be connected to system ground. Minimize the
ground path impedance for optimal performance of
the device.
External Biasing Resistor.
Used by on-chip circuitry to establish bias currents
within the device. This pin must be connected to
GND through a 10 k Ω (1%) resistor.
Reserved—No Connect.
This pin must be left unconnected for normal
operation.
Reserved—GND.
This pin must be tied to GND for normal operation.
Description
Si5321
29

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