SI5321-H-BL Silicon Laboratories Inc, SI5321-H-BL Datasheet - Page 28

• Manufacturer Part Number: SI5321-H-BL
• Description: IC CLOCK MULT SONET/SDH 63-PBGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5321-H-BL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5321
28
*Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a
D3–D5,
E3–E5
Pin #
H4
H3
D8
E8
C2
F8
logic low state if the input is not driven from an external source.
CAL_ACTV
RSTN/CAL
DH_ACTV
Pin Name
VALTIME
VSEL33
V
LOS
DD33
Table 10. Si5321 Pin Descriptions (Continued)
V
I/O
O
O
O
I*
I*
I*
DD
Signal Level
LVTTL*
LVTTL*
LVTTL*
Supply
LVTTL
LVTTL
LVTTL
Rev. 2.5
Clock Validation Time for LOS.
VALTIME sets the clock validation times for recovery
from an LOS alarm condition. When VALTIME is
high, the validation time is approximately 100 ms.
When VALTIME is low, the validation time is approx-
imately 2 ms.
Reset/Calibrate.
When low, all LVTTL outputs are forced into a high
impedance state, the DSPLL is forced out-of-lock,
and the device control logic is reset.
A low-to-high transition on RSTN/CAL initializes all
digital logic to a known condition and initiates self-
calibration of the DSPLL. At the completion of self-
calibration, the DSPLL begins to lock to the selected
clock input signal and begins to drive out the output
clock signal onto the CLKOUT pins.
Loss-of-Signal (LOS) Alarm for CLKIN.
Active high output indicates that the Si5321 has
detected missing pulses on the input clock signal.
The LOS alarm is cleared after either 100 ms or 13 s
of a valid CLKIN clock input, depending on the set-
ting of the VALTIME input.
Digital Hold Mode Active.
Active high output indicates that the DSPLL is in
digital hold mode. Digital hold mode locks the
current state of the DSPLL and forces the DSPLL to
continue generation of the output clock with no
additional phase or frequency information from the
input clock.
Calibration Mode Active.
This output is driven high during the DSPLL self-cal-
ibration and the subsequent initial lock acquisition
period.
Reserved.
This pin must be tied to VDD33 directly for normal
operation.
3.3 V Supply.
3.3 V power is applied to the V
supply bypassing/decoupling for this configuration is
indicated in the typical application diagram for 3.3 V
supply operation.
Description
DD33
pins. Typical