MSC8144VT800A Freescale Semiconductor, MSC8144VT800A Datasheet - Page 50

• Manufacturer Part Number: MSC8144VT800A
• Description: IC DSP QUAD 800MHZ 783FCBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC3400 Corer

Specifications of MSC8144VT800A

• Interface: Ethernet, I²C, SPI, TDM, UART, UTOPIA
• Clock Rate: 800MHz
• Non-volatile Memory: External
• On-chip Ram: 10.5MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.00V
• Operating Temperature: 0°C ~ 90°C
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Characteristics
2.6.5.8
For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point at (baud
frequency)/1667 is applied to the jitter. The data pattern for template measurements is the continuous jitter test pattern (CJPAT)
defined in Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive
directions, and opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined
in Annex 48A. Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0.
The amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10
shall be measured with AC coupling and the compliance template centered at 0 Volts differential. The left and right edges of
the template shall be aligned with the mean zero crossing points of the measured data eye. The load for this test shall be 100 Ω
resistive
2.6.5.9
For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (baud frequency)/1667 is
applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter Test Pattern (CJPAT) pattern defined in
Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and
opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A.
Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be
measured with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter tolerance
setup) shall be performed with a test procedure resulting in a BER curve such as that described in Annex 48B of IEEE Std.
802.3ae.
2.6.5.10
Transmit jitter is measured at the driver output when terminated into a load of 100 Ω resistive
2.6.5.11
Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first producing the sum
of deterministic and random jitter defined in Section 2.6.5.9 and then adjusting the signal amplitude until the data eye contacts
the 6 points of the minimum eye opening of the receive template shown in
the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter)
about the mean zero crossing. Eye template measurement requirements are as defined above. Random jitter is calibrated using
a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter
specified in Section 8.6 is then added to the signal and the test load is replaced by the receiver being tested.
2.6.6
This section describes the general AC timing parameters of the PCI bus.
50
Output delay
High-Z to Valid Output delay
Valid to High-Z Output delay
Input setup
Input hold
±
5% differential to 2.5 GHz.
PCI Timing
Eye Template Measurements
Jitter Test Measurements
Transmit Jitter
Jitter Tolerance
Parameter
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Table 36. PCI AC Timing Specifications
Symbol
t
t
t
PCOFF
t
PCVAL
PCON
t
PCSU
PCH
Min
2.0
2.0
7.0
—
0
33 MHz
Table 36
Figure 14
Max
11.0
28
—
—
—
provides the PCI AC timing specifications.
and
Table
Min
1.0
1.0
3.0
—
0
±
5% differential to 2.5 GHz.
35. Note that for this to occur,
66 MHz
Freescale Semiconductor
Max
6.0
14
—
—
—
–12
. The eye pattern
Unit
ns
ns
ns
ns
ns