MSC8144VT800A Freescale Semiconductor, MSC8144VT800A Datasheet - Page 78

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MSC8144VT800A

Manufacturer Part Number
MSC8144VT800A
Description
IC DSP QUAD 800MHZ 783FCBGA
Manufacturer
Freescale Semiconductor
Series
MSC81xx StarCorer
Type
SC3400 Corer
Datasheet

Specifications of MSC8144VT800A

Interface
Ethernet, I²C, SPI, TDM, UART, UTOPIA
Clock Rate
800MHz
Non-volatile Memory
External
On-chip Ram
10.5MB
Voltage - I/o
3.30V
Voltage - Core
1.00V
Operating Temperature
0°C ~ 90°C
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Revision History
7
Table 66
78
Rev.
0
1
2
3
4
5
6
June 2007 • Corrected AA4 definition in
Feb. 2007
Apr. 2007
Sep 2007
Sep 2007
provides a revision history for this data sheet.
Oct 2007
Oct 2007
Revision History
Date
• Initial public release.
• Adds new I/O multiplexing mode 7 that supports POS functionality.
• Updates reference voltage supply for pins G5, H7, and H8 in
• Updates start-up timing recommendations with regard to TRST and M3_RESET in Section 2.7.1.
• Adds input clock duty cycles in
• Updates PCI AC timings in
• Removes UTOPIA internal clock specifications in
• Updates JTAG timings in
• Clarifies connectivity guidelines for Ethernet pins in Section 3.3.4.
• Miscellaneous pin connectivity guidelines were updated in
• Updates name of core subsystem reference manual.
• Removed Figure 35 because the device does not support UTOPIA using an internal clock. Renumbered
• Removed Section 3.5 Thermal Considerations. To be replaced with an application note.
• Updated M3 voltage range in
• Changed note in
• DDR voltage designator changed from V
• Deleted text before
• Deleted text before
• Deleted Section 2.6.5 on page 32 and renumbered subsequent subsections.
• Deleted text before new Section 2.6.5.1.
• Added a 1 to the note in
• Deleted ac voltage rows from
• Changed output high and low voltage levels in
• Deleted text before
• Added clock skew ranges in percent in
• Changed V
• Changed V
• Added note 4 to
• Changed V
• Changed the value of the data to clock out skew in
• Changed EE pin timing in
• Changed the head for the JTAG timing section, now Section 2.7.15.
• Updated JTAG timing for TCK cycle time, TCK high phase, and boundary scan input data hold time in
• Added new Section 3.3 with guidelines for board layout for clock and timing signals. Renumbered subsequent
• Changed leakage current values in
• Change the minimum value of t
• Updated note 1 in
• Corrected column numbering in
• Updated SPI signal names in
• Updated SPI signal names in
subsequent figures.
and
sections.
from –10 and 10 μa to –30 and 30 μa.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Figure
REF
DD
DD
11. Changed range on I
to V
to V
to MV
Table
Table 66. Document Revision History
Table 7
Table
DDIO
DDGE
Table 13
Table
Table
REF
42. Changed t
Table 15
45.
in
for PLL power supplies.
in
14, added a 1 to the note, and added note 1 to input pin capacitance.
19.
Table
in Table 26.
Table
Table 41
Figure 27
Table
Table
and added note 2 to input pin capacitance.
Table
Table
Table
Table
MDDVKH
Table
56.
Figure 3
55.
and added note 1 to input pin capacitance.
41.
OZ
1. Changed TDM5TD3 to correct name TDM5TDAT.
Table
1.
1.
3.
16. Added note 1 to input pin capacitance.
Updated note 2.
TDMSHOX
in
and
20.
Table
Table 8
DD
13,
in
and
Figure
Table 45
to V
Table
21.
Figure
Description
Table 17
value.
and
DDDDR
30.
Table
14,
Table
Table
4.
from 5 ns to 7 ns.
Table
in
and
52.
51.
10.
Table
Table
Table
11,
Table
Table
8,
71.
18.
1.
Table
16,
10, Section 2.7.4.1, Section 2.7.4.2,
Table
17,
Freescale Semiconductor
Table
18, and
Table 19
Table
56.

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