74AUP2G38GD,125 NXP Semiconductors, 74AUP2G38GD,125 Datasheet - Page 21
![IC GATE NAND DUAL INPUT XSON8U](/photos/39/72/397248/inhouse_4aup2g38gd125_t_sml.jpg)
74AUP2G38GD,125
Manufacturer Part Number
74AUP2G38GD,125
Description
IC GATE NAND DUAL INPUT XSON8U
Manufacturer
NXP Semiconductors
Datasheet
1.74AUP2G38GD125.pdf
(21 pages)
Specifications of 74AUP2G38GD,125
Product
NAND
Number Of Gates
2
Propagation Delay Time
4.9 ns, 6.5 ns, 8.2 ns, 12.6 ns
Supply Voltage (max)
4.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
XSON-8U
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-5411-2
NXP Semiconductors
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Low-power dual 2-input NAND gate; open drain
74AUP2G38
Date of release: 23 September 2010
Document identifier: 74AUP2G38
All rights reserved.