W25Q64CVSSIG Winbond Electronics, W25Q64CVSSIG Datasheet
W25Q64CVSSIG
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W25Q64CVSSIG Summary of contents
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... SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI Publication Release Date: January 4, 2010 - 1 - Preliminary - Revision B W25Q64CV ...
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... Sector/Block Protect (SEC) ................................................................................................13 11.1.6 Complement Protect (CMP) ...............................................................................................14 11.1.7 Status Register Protect (SRP1, SRP0)...............................................................................14 11.1.8 Erase/Program Suspend Status (SUS) ..............................................................................14 11.1.9 Security Register Lock Bits (LB3, LB2, LB1, LB0) ..............................................................14 11.1.10 Quad Enable (QE) ............................................................................................................15 11.1.11 Status Register Memory Protection (CMP = 0).................................................................16 Table of Contents - 2 - W25Q64CV ...
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... Status Register Memory Protection (CMP = 1).................................................................17 11.2 INSTRUCTIONS................................................................................................................. 18 11.2.1 Manufacturer and Device Identification ..............................................................................18 11.2.2 Instruction Set Table 1 (Erase, Program Instructions) ........................................................19 11.2.3 Instruction Set Table 2 (Read Instructions) ........................................................................20 11.2.4 Instruction Set Table 3 (ID, Security Instructions)...............................................................21 11.2.5 Write Enable (06h)..............................................................................................................22 11.2.6 Write Enable for Volatile Status Register (50h) ..................................................................22 11 ...
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ELECTRICAL CHARACTERISTICS .............................................................................................. 59 12.1 Absolute Maximum Ratings................................................................................................ 59 12.2 Operating Ranges .............................................................................................................. 59 12.3 Power-up Timing and Write Inhibit Threshold .................................................................... 60 12.4 DC Electrical Characteristics.............................................................................................. 61 12.5 AC Measurement Conditions ............................................................................................. 62 12.6 AC Electrical Characteristics .............................................................................................. ...
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... Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation. ...
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PIN CONFIGURATION SOIC 208-MIL Figure 1a. W25Q64CV Pin Assignments, 8-pin SOIC 208-mil (Package Code SS) 4. PAD CONFIGURATION WSON 6X5-MM / 8X6-MM Figure 1b. W25Q64CV Pad Assignments, 8-pad WSON (Package Code ZP & ZE W25Q64CV ...
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PAD CONFIGURATION PDIP 300-MIL Figure 1c. W25Q64CV Pin Assignments, 8-pin PDIP (Package Code DA) 6. PIN DESCRIPTION SOIC 208-MIL, WSON 6X5/8X6-MM AND PDIP 300-MIL PIN NO. PIN NAME 1 / (IO1) 3 /WP (IO2) 4 GND 5 ...
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PIN CONFIGURATION SOIC 300-MIL Figure 1d. W25Q64CV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 8. PIN DESCRIPTION SOIC 300-MIL PAD NO. PAD NAME 1 /HOLD (IO3) 2 VCC 3 N/C 4 N/C 5 N/C 6 N/C 7 /CS ...
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... Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin function is not available since this pin is used for IO2 ...
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... CLK SPI SPI /CS /CS Command & Command & Control Logic Control Logic DI ( ( Figure 2. W25Q64CV Serial Flash Memory Block Diagram xxFFFFh xxFFFFh • • xxF0FFh xxF0FFh xxEFFFh xxEFFFh • • xxE0FFh xxE0FFh xxDFFFh xxDFFFh • • xxD0FFh xxD0FFh xx2FFFh xx2FFFh • ...
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FUNCTIONAL DESCRIPTION 10.1 SPI OPERATIONS 10.1.1 Standard SPI Instructions The W25Q64CV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI ...
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... Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC,TB, BP2, BP1 and BP0) bits. These settings allow a portion as small as 4KB sector or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control ...
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... The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits ...
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... CMP=0, a top 4KB sector can be protected while the rest of the array is not; when CMP=1, the top 4KB sector will become unprotected while the rest of the array become read-only. Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0. 11.1.7 Status Register Protect (SRP1, SRP0) The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8 and S7) ...
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Quad Enable (QE) The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI operation. When the QE bit is set state (factory default), the /WP pin and ...
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... Status Register Memory Protection (CMP = 0) (1) STATUS REGISTER SEC TB BP2 BP1 BP0 Note don’t care Lower Upper W25Q64CV (64M-BIT) MEMORY PROTECTION PROTECTED PROTECTED BLOCK(S) ADDRESSES NONE NONE 126 & 127 7E0000h – 7FFFFFh 124 ~ 127 7C0000h – 7FFFFFh 120 ~ 127 780000h – ...
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... Status Register Memory Protection (CMP = 1) (1) STATUS REGISTER SEC TB BP2 BP1 BP0 Note don’t care Lower Upper W25Q64CV (64M-BIT) MEMORY PROTECTION UNPROTECTED UNPROTECTED BLOCK(S) ADDRESSES NONE NONE 126 & 127 7E0000h – 7FFFFFh 124 ~ 127 7C0000h – 7FFFFFh 120 ~ 127 780000h – ...
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... This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed ...
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Instruction Set Table 1 (Erase, Program Instructions) BYTE 1 INSTRUCTION NAME (CODE) Write Enable 06h Write Enable for Volatile 50h Status Register Write Disable 04h Read Status Register-1 05h Read Status Register-2 35h Write Status Register 01h Page Program ...
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Instruction Set Table 2 (Read Instructions) BYTE 1 INSTRUCTION NAME (CODE) Read Data 03h Fast Read 0Bh Fast Read Dual Output 3Bh Fast Read Quad Output 6Bh Fast Read Dual I/O BBh Fast Read Quad I/O EBh (7) Word ...
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... Please note that Security Register 0 is Reserved by Winbond for future use recommended to use Security registers 1- 3 before using register 0 BYTE 2 BYTE 3 dummy dummy dummy dummy A23-A8 A7-A0, M[7:0] xxxx, (MF[7:0], ID[7:0]) (MF7-MF0) (ID15-ID8) Manufacturer Memory Type dummy dummy A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15– W25Q64CV BYTE 4 BYTE 5 ...
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... The non-volatile Status Register bits described in section 11.1 can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non- volatile bits ...
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Write Disable (04h) The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into ...
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Read Status Register-1 (05h) and Read Status Register-2 (35h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 ...
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To complete the Write Status Register instruction, the /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be executed. ...
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... DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high. ...
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Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of F (see AC Electrical Characteristics). This is accomplished by adding eight R “dummy” clocks ...
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Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; IO twice the rate of standard SPI devices. The Fast ...
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Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on four pins, IO executed before the device will accept the Fast ...
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Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO and similar to the Fast Read Dual Output (3Bh) instruction but with ...
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Figure 13b. Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10) Publication Release Date: January 4, 2010 - 31 - W25Q64CV Preliminary - Revision B ...
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Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO clock are required ...
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Figure 14b. Fast Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” The Fast Read Quad I/O instruction can also be used to access a specific portion within a page ...
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Word Read Quad I/O (E7h) The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lowest Address bit (A0) must equal 0 and only two Dummy clock are required ...
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Figure 15b. Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” The Word Read Quad I/O instruction can also be used to access a specific portion within a page ...
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Octal Word Read Quad I/O (E3h) The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As ...
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Figure 16b. Octal Word Read Quad I/O Instruction Sequence (Previous instruction set M5 ...
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Set Burst with Wrap (77h) The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and “Word Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. ...
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... The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O”, “Fast Read Quad I/O”, “Word Read Quad I/O” and “Octal Word Read Quad I/O” instructions to provide the highest random Flash memory access rate with minimum SPI instruction overhead, thus allow true XIP (execute in place performed on serial flash devices. ...
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... Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “ ...
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... Quad Input Page Program (32h) The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO improve performance for PROM Programmer and applications that have slow clock speeds <5MHz. Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent page program time is much greater than the time it take to clock-in the data ...
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... Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Chip Erase (C7h / 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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Erase / Program Suspend (75h) The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase operation or a Page Program operation and then read from or program/erase data to, any other sectors or blocks. ...
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Erase / Program Resume (7Ah) The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah” will be accepted by the ...
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Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ...
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Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number. To ...
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Figure 29. Release Power-down / Device ID Instruction Sequence Diagram - 50 - W25Q64CV ...
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Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ...
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Read Manufacturer / Device ID Dual I/O (92h) The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific ...
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Read Manufacturer / Device ID Quad I/O (94h) The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific ...
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Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q64CV device. The ID number can be used in conjunction with user software methods to help prevent ...
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... The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 34. For memory type and capacity values refer to Manufacturer and Device Identification table. ...
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... The W25Q64CV offers four 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction must be executed before the device will accept the Erase Security Register Instruction (Status Register bit WEL must equal 1) ...
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... Program Security Registers (42h) The Program Security Register instruction is similar to the Page Program instruction. It allows from one byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Program Security Register Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “ ...
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... DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is automatically incremented to the next byte address after each byte of data is shifted out ...
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ELECTRICAL CHARACTERISTICS 12.1 Absolute Maximum Ratings PARAMETERS Supply Voltage Voltage Applied to Any Pin Transient Voltage on any Pin Storage Temperature Lead Temperature Electrostatic Discharge Voltage Notes: 1. Specification for W25Q64CV is preliminary. See preliminary designation at the end ...
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Power-up Timing and Write Inhibit Threshold PARAMETER VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. SYMBOL MIN t (1) VSL t (1) PUW V 1.0 (1) ...
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DC Electrical Characteristics PARAMETER SYMBOL IN (1) Input Capacitance C (1) Output Capacitance Cout Input Leakage I LI I/O Leakage I LO Standby Current Power-down Current Current Read Data / ...
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AC Measurement Conditions PARAMETER Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. SYMBOL ...
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AC Electrical Characteristics DESCRIPTION Clock frequency for all instructions, except Read Data (03h) & Octal Word Read (E3h) 2.7V-3.6V VCC & Industrial Temperature Clock frequency for Octal Word Read Quad I/O (E3h) 3.0V-3.6V VCC & Industrial Temperature Clock freq. ...
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AC Electrical Characteristics ( DESCRIPTION /HOLD Active Hold Time relative to CLK /HOLD Not Active Setup Time relative to CLK /HOLD Not Active Hold Time relative to CLK /HOLD to Output Low-Z /HOLD to Output High-Z Write Protect Setup ...
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Serial Output Timing 12.9 Input Timing 12.10 Hold Timing Publication Release Date: January 4, 2010 - 65 - W25Q64CV Preliminary - Revision B ...
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PACKAGE SPECIFICATION 13.1 8-Pin SOIC 208-mil (Package Code SS) SYMBOL MIN A 1.75 A1 0.05 A2 1.70 b 0.35 C 0.19 D 5.18 D1 5.13 E 5. 7. θ 0° Notes: ...
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PDIP 300-mil (Package Code DA Symbol Min A --- A1 0.25 A2 3.18 B 0.41 B1 1. ...
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WSON (Package Code ZP) SYMBOL MIN A 0.70 A1 0. 5.90 D2 3.35 4. (2) L 0.55 y 0.00 MILLIMETERS TYP. MAX MIN 0.75 0.80 0.0275 0.02 0.05 ...
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WSON 6x5mm Cont’d. SYMBOL SOLDER PATTERN Notes: 1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E ...
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WSON (Package Code ZE) MILLIMETERS SYMBOL MIN A 0.70 A1 0.00 b 0.35 C 0.19 D 7.90 D2 4.60 E 5. 0.45 TYP. MAX MIN 0.75 0.80 0.02755 0.02 0.05 0.0000 0.40 0.48 ...
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SOIC 300-mil (Package Code SF) SYMBOL MIN A 2. 0.33 C 0.18 D 10.08 E 10. 0.38 y θ Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC ...
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... ORDERING INFORMATION W = Winbond 25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O 64C = 64M-bit V = 2. 8-pin SOIC 208-mil SF = 16-pin SOIC 300-mil I = Industrial (-40°C to +85°C) ( Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Green Package with Status Register Power-Down & OTP enabled ...
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... Notes: 1. For WSON packages, the package type ZP and ZE are not used in the top side marking. 2. Package type ZE (WSON-8 8x6mm special order package, please contact Winbond for ordering information. PRODUCT NUMBER TOP SIDE MARKING W25Q64CVSSIG W25Q64CVSSIP W25Q64CVSFIG W25Q64CVSFIP W25Q64CVDAIG W25Q64CVDAIP W25Q64CVZPIG W25Q64CVZPIP ...
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... Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Winbond products are not designed, intended, authorized or warranted for use as components in systems ...