PC28F256P30B85D NUMONYX, PC28F256P30B85D Datasheet - Page 50
![IC FLASH 256MBIT 85NS 64EZBGA](/photos/7/31/73106/pc28f256p30b85_s_l9c4_sml.jpg)
PC28F256P30B85D
Manufacturer Part Number
PC28F256P30B85D
Description
IC FLASH 256MBIT 85NS 64EZBGA
Manufacturer
NUMONYX
Series
StrataFlash™r
Datasheet
1.RD48F4400P0VBQEJ.pdf
(97 pages)
Specifications of PC28F256P30B85D
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
256M (16Mx16)
Speed
85ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
880699
880699TR
880699TR
PC28F256P30B85 S L9C4
PC28F256P30B85DTR
880699TR
880699TR
PC28F256P30B85 S L9C4
PC28F256P30B85DTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PC28F256P30B85D
Manufacturer:
Micron Technology Inc
Quantity:
10 000
12.0
12.1
12.2
Table 23: Reset Specifications
Datasheet
50
Notes:
1.
2.
3.
4.
5.
6.
7.
Num
P1
P2
P3
t
t
t
These specifications are valid for all device versions (packages and speeds).
The device may reset if t
Not applicable if RST# is tied to Vcc.
Sampled, but not 100% tested.
When RST# is tied to the V
When RST# is tied to the V
Reset completes within t
Symbol
PLPH
PLRH
VCCPH
Power and Reset Specifications
Power-Up and Power-Down
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
V
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
CC
RST# pulse width low
RST# low to device reset during erase
RST# low to device reset during program
V
V
CC
CC
and V
Power valid to RST# de-assertion (high) 130nm
Power valid to RST# de-assertion (high) 65nm
CCQ
PLPH
PLPH
should attain their minimum operating voltage before applying V
CC
CCQ
if RST# is asserted while no erase or program operation is executing.
is < t
supply, device will not be ready until t
supply, device will not be ready until t
Parameter
PLPH MIN
, but this is not guaranteed.
VCCPH
VCCPH
Min
100
300
60
-
-
after V
after V
CC
CC
Max
≥ V
25
25
≥ V
-
-
-
CCMIN
CCMIN
.
.
Unit
ns
µs
August 2008
306666-12
PP
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
1,4,5,6
Notes
.
P30