PC28F256P30B85D NUMONYX, PC28F256P30B85D Datasheet - Page 59
![IC FLASH 256MBIT 85NS 64EZBGA](/photos/7/31/73106/pc28f256p30b85_s_l9c4_sml.jpg)
PC28F256P30B85D
Manufacturer Part Number
PC28F256P30B85D
Description
IC FLASH 256MBIT 85NS 64EZBGA
Manufacturer
NUMONYX
Series
StrataFlash™r
Datasheet
1.RD48F4400P0VBQEJ.pdf
(97 pages)
Specifications of PC28F256P30B85D
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
256M (16Mx16)
Speed
85ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
880699
880699TR
880699TR
PC28F256P30B85 S L9C4
PC28F256P30B85DTR
880699TR
880699TR
PC28F256P30B85 S L9C4
PC28F256P30B85DTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PC28F256P30B85D
Manufacturer:
Micron Technology Inc
Quantity:
10 000
P30
Table 31: AC Read Specifications for 256/512-Mbit Densities (Sheet 3 of 3)
Table 32: AC Read Specification differences for 65nm
August 2008
Order Number: 306666-12
R301
R302
R303
R304
R305
R306
R307
R311
R312
Notes:
1.
2.
3.
4.
5.
6.
7.
Asynchronous Specifications
Notes:
1.
2.
Num
Num
R103
R1
R2
R3
See
allowable input slew rate.
OE# may be delayed by up to t
Sampled, not 100% tested.
Address hold in synchronous burst mode is t
Please see the latest P30 Spec Update for synchronous burst operation with the TSOP package .
Synchronous read mode is not supported with TTL level inputs.
Applies only to subsequent synchronous reads.
See
max allowable input slew rate.
This is the recommended specification for all new designs supporting both 130nm and 65nm lithos, or for new designs
that will use the 65nm lithography.
t
t
t
t
t
t
t
t
t
ADV# low to output valid
AVCH/L
VLCH/L
ELCH/L
CHQV / tCLQV
CHQX
CHAX
CHTV
CHVL
CHTX
Figure 18, “AC Input/Output Reference Waveform” on page 55
Figure 18, “AC Input/Output Reference Waveform” on page 55
Symbol
Symbol
t
t
t
AVAV
AVQV
ELQV
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
CLK Valid to ADV# Setup
WAIT Hold from CLK
Read cycle time
Address to output valid
CE# low to output valid
t
VLQV
Parameter
ELQV
– t
GLQV
Parameter
after CE#’s falling edge without impact to t
CHAX
or t
VHAX
, whichever timing specification is satisfied first.
Speed
TSOP
TSOP
TSOP
TSOP
Min
100
110
Min
-
-
-
10
9
9
9
3
3
3
-
-
for timing measurements and max
for timing measurements and
ELQV.
Max
100
110
100
110
100
110
Max
-
17
17
-
-
-
-
-
-
-
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Datasheet
Notes
1,2
1,4,7
2
2
2
2
2
2
2
1,7
1,7
1,7
1
1
59