LM25066APSQE/NOPB National Semiconductor, LM25066APSQE/NOPB Datasheet - Page 16

• Manufacturer Part Number: LM25066APSQE/NOPB
• Description: IC CTLR PM HOTSWAP 24-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM25066APSQE/NOPB

• Applications: Base Station-Networking Line Cards, Servers
• Current - Supply: 5.8mA
• Voltage - Supply: 2.9 V ~ 17 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Input Voltage: 17V
• Internal Switch: No
• Supply Voltage Range: 2.9V To 5.5V
• Rohs Compliant: Yes
• Digital Ic Case Style: LLP
• No. Of Pins: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM25066APSQE/NOPBTR

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Under-Voltage Lockout (UVLO)
The series pass MOSFET (Q
supply voltage (V
the programmable under-voltage lockout (UVLO) and over-
voltage lockout (OVLO) levels. Typically the UVLO level at
V
5. Refering to the Block Diagram when V
LO level, the internal 23 µA current source at UVLO is en-
abled, the current source at OVLO is off, and Q
the 2 mA pull-down current at the GATE pin. As V
creased, raising the voltage at UVLO above its threshold the
23 µA current source at UVLO is switched off, increasing the
voltage at UVLO, providing hysteresis for this threshold. With
the UVLO/EN pin above its threshold, Q
the 22 µA current source at the GATE pin if the insertion time
delay has expired.
See the Applications Section for a procedure to calculate the
values of the threshold setting resistors (R1-R3). The mini-
mum possible UVLO level at V
the UVLO/EN pin to VIN. In this case Q
insertion time when the voltage at VIN reaches the POR
threshold. After power up, an UVLO condition will toggle high
the VIN UV FAULT bit high in the STATUS_INPUT (7Ch)
register, the INPUT bit in the STATUS_WORD (79h) register,
and
DIAGNOSTIC_WORD (E1h) registers, and SMBA pin will be
pulled low unless this feature is disabled using the
ALERT_MASK (D8h) register.
Over-Voltage Lockout (OVLO)
The series pass MOSFET (Q
supply voltage (V
the programmable under-voltage lockout (UVLO) and over-
voltage lockout (OVLO) levels. If V
voltage above its threshold, Q
pull-down current at the GATE pin, denying power to the load.
When the OVLO pin is above its threshold, the internal 23 µA
current source at OVLO is switched on, raising the voltage at
OVLO to provide threshold hysteresis. When V
below the OVLO level, Q
will toggle high the VIN OV FAULT bit high in the STATUS_IN-
PUT (7Ch) register, the INPUT bit in the STATUS_WORD
(79h) register, and the VIN_OVERVOLTAGE_FAULT bit in
the DIAGNOSTIC_WORD (E1h) registers, and the SMBA pin
SYS
is set with a resistor divider (R1-R3) as shown in
the
VIN_UNDERVOLTAGE_FAULT
SYS
SYS
) is within the operating range defined by
) is within the operating range defined by
1
is re-enabled. An OVLO condition
1
1
1
SYS
) is enabled when the input
) is enabled when the input
is switched off by the 2 mA
can be set by connecting
SYS
raises the OVLO pin
1
SYS
1
is enabled after the
is switched on by
is below the UV-
SYS
1
bit
is held off by
FIGURE 4. Restart Sequence
is reduced
SYS
in
Figure
is in-
the
16
will be pulled low unless this feature is disabled using the
ALERT_MASK (D8h) register.
See the Applications Section for a procedure to calculate the
threshold setting resistor values.
Shutdown Control
The load current can be remotely switched off by taking the
UVLO/EN pin below its threshold with an open collector or
open drain device, as shown in
UVLO/EN pin, the LM25066A switches on the load current
with inrush current and power limiting.
Power Good
The Power Good indicator (PGD) is connected to the drain of
an internal N-channel MOSFET capable of sustaining 17V in
the off-state, and transients up to 20V. An external pull-up
resistor is required at PGD to an appropriate voltage to indi-
cate the status to downstream circuitry. The off-state voltage
at the PGD pin can be higher or lower than the voltages at
VIN and OUT. PGD is switched high when the voltage at the
FB pin exceeds the PGD threshold voltage. Typically the out-
put voltage threshold is set with a resistor divider from output
to feedback, although the monitored voltage need not be the
output voltage. Any other voltage can be monitored as long
as the voltage at the FB pin does not exceed its maximum
rating. Referring to the Block Diagram, when the voltage at
the FB pin is below its threshold, the 24 µA current source at
FB is disabled. As the output voltage increases, taking FB
FIGURE 5. Shutdown Control
Figure
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5. Upon releasing the
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