ISL6267HRZ-T Intersil, ISL6267HRZ-T Datasheet - Page 7

• Manufacturer Part Number: ISL6267HRZ-T
• Description: IC PWM CTRLR MULTIPHASE 48TQFN
• Manufacturer: Intersil

Specifications of ISL6267HRZ-T

• Applications: Converter, AMD Fusion™ CPU GPU
• Voltage - Input: 4.75 V ~ 5.25 V
• Number Of Outputs: 2
• Voltage - Output: 0.0125 V ~ 1.55 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Configuration
Pin Descriptions
PIN NUMBER
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
PGOOD_NB
COMP_NB
SYMBOL
FB2_NB
PWROK
ENABLE
VR_HOT
VW_NB
PGOOD
FB_NB
COMP
SVD
SVC
NTC
VW
FB
7
PGOOD_NB
COMP_NB
ENABLE
VR_HOT
FB2_NB
PWROK
PGOOD
VW_NB
FB_NB
The components connecting to FB2_NB are used to adjust the compensation in 1-phase mode to achieve
optimum performance.
Output voltage feedback to the inverting input of the Northbridge controller error amplifier.
Northbridge VR error amplifier output.
Window voltage set pin used to set the switching frequency for the Northbridge controller. A resistor from
this pin to COMP_NB programs the switching frequency (8kΩ gives approximately 300kHz).
Open-drain output to indicate the Northbridge portion of the IC is ready to supply regulated voltage. Pull-
up externally to VCCP or 3.3V.
Serial VID data bi-directional signal from the CPU processor master device to the VR.
System power good input. When this pin is high, the SVI interface is active and the I
While this pin is low, the SVC and SVD input states determine the pre-PWROK metal VID. This pin must
be low prior to the ISL6267 PGOOD output going high per the AMD SVI Controller Guidelines.
Serial VID clock input from the CPU processor master device.
Enable input. A high level logic on this pin enables both VRs.
Open-drain output to indicate the Core portion of the IC is ready to supply regulated voltage. Pull up
externally to VCCP or 3.3V.
Thermal overload open drain output indicator active LOW.
Thermistor input to VR_HOT circuit to monitor Core VR temperature.
Window voltage set pin used to set the switching frequency for the Core controller. A resistor from this
pin to COMP programs the switching frequency (8kΩ gives approximately 300kHz).
Error amplifier output.
Output voltage feedback to the inverting input of the Core controller error amplifier.
SVD
SVC
NTC
10
11
12
3
4
5
6
7
8
9
1
2
48
47 46 45 44 43 42 41 40 39 38 37
ISL6267
(48 LD QFN)
TOP VIEW
ISL6267
(BOTTOM)
GND PAD
DESCRIPTION
37
36 PWM2_NB
35 BOOT2
34 UG2
33 PH2
32 LG2
31 VCCP
30 PWM3
29 LG1
28 PH1
27 UG1
26 BOOT1
25 PROG1
2
C protocol is running.
January 31, 2011
FN7801.0