ISL6267 INTERSIL [Intersil Corporation], ISL6267 Datasheet

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... The two VRs share the serial control bus to communicate with the CPU and achieve lower cost and smaller board area compared with two-chip solutions. The PWM modulator of ISL6267 is based on Intersil’s R3 (Robust Ripple Regulator) Technology™. Compared with the traditional multi-phase buck regulator, the R3 modulator commands variable switching frequency during load transients, achieving faster transient response ...

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... FIGURE 3. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING 2 ISL6267 BOOT_NB UG1_NB ISEN1_NB PH1_NB ISEN2_NB LG1_NB ISUMN_NB ISUMP_NB VW_NB PWM2_NB COMP_NB NTC_NB FB_NB FB2_NB PROG1 PROG2 VSEN_NB VR_HOT RTN_NB ISL6267 NTC PWROK SVD SVC PWM3 VW VW COMP COMP BOOT2 FB FB UG2 VSEN VSEN PH2 RTN LG2 ISEN3 BOOT1 ISEN2 ...

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... FIGURE 4. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING 3 ISL6267 NTC_NB ISEN1_NB BOOT_NB ISEN2_NB UG1_NB ISUMN_NB PH1_NB ISUMP_NB LG1_NB VW_NB COMP_NB PWM2_NB FB_NB FB2_NB VSEN_NB NTC RTN_NB VR_HOT ISL6267 PROG1 PWROK PROG2 SVD SVC PWM3 VW VW BOOT2 COMP COMP UG2 PH2 FB ISEN3/FB2 LG2 VSEN VSEN RTN BOOT1 ...

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... ISEN1_NB BOOT_NB UG1_NB ISUMN_NB PH1_NB ISUMP_NB LG1_NB NTC_NB VW_NB PWM2_NB OPEN COMP_NB FB_NB PROG1 VSEN_NB PROG2 RTN_NB NTC VR_HOT PWROK SVD ISL6267 SVC PWM3 BOOT2 OPEN ISEN1 UG2 OPEN ISEN2 PH2 OPEN ISEN3 VW VW LG2 OPEN PGND2 COMP COMP OPEN BOOT1 ...

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... ISUMN ISUMP FIGURE 6. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING 5 ISL6267 BOOT_NB UG1_NB PH1_NB LG1_NB NTC_NB OPEN PWM2_NB PROG1 PROG2 NTC VR_HOT Thermal Indicator ISL6267 PWM3 +5V BOOT2 OPEN UG2 OPEN PH2 OPEN OPEN LG2 PGND2 OPEN BOOT1 UG1 PH1 LG1 VIN ...

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... TEMP NTC MONITOR VR_HOT VW DAC1 + + RTN E COMP + ISUMP ISUMN - VSEN 6 ISL6267 PROG1 PROG2 A/D VCORE VNB DAC1 DAC1 (SIMILAR ARCHITECTURE TO DAC2 DAC2 T_MONITOR MODULATOR OC AND WOC CURRENT CURRENT PROTECTION SENSE SENSE OV PROTECTION NORTHBRIDGE CONTROLLER AND DRIVER CORE SECTION) PHASE PHASE IBAL ...

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... While this pin is low, the SVC and SVD input states determine the pre-PWROK metal VID. This pin must be low prior to the ISL6267 PGOOD output going high per the AMD SVI Controller Guidelines. Serial VID clock input from the CPU processor master device. ...

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... When the Core VR of ISL6267 is configured in 3-phase mode, this pin is ISEN3. ISEN3 is the individual current sensing for Channel 3. When the Core VR of ISL6267 is configured in 2-phase mode, this pin is FB2. There is a switch between the FB2 pin and the FB pin. The switch 2-phase mode and is off in 1-phase mode ...

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... RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6267. For more information on MSL please see tech brief TB363. 9 ISL6267 Connect an MLCC capacitor across the BOOT1_NB and the PH1_NB pins ...

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... Table of Contents Core Performance On ISL6267EVAL1Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Simplified Application Circuit For High Power CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Simplified Application Circuit For AMD Torpedo Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Simplified Application Circuit For Low Power CPU Core And Simplified Application Circuit Showing Resistor Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Descriptions Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal Information ...

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... Adjustment Range AMPLIFIERS Current-Sense Amplifier Input Offset Error Amp DC Gain Error Amp Gain-Bandwidth Product 11 ISL6267 Thermal Information Thermal Resistance (Typical QFN Package (Notes Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C Maximum Junction Temperature (Plastic Package .+150°C Storage Temperature Range .-65° ...

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... PWM PWM Output Low PWM Output High PWM Tri-State Leakage THERMAL MONITOR NTC Source Current NTC_NB Source Current Thermal Monitor Trip Voltage Thermal Monitor Reset Voltage 12 ISL6267 = 5V -10°C to +100° SYMBOL TEST CONDITIONS Maximum of ISENs - Minimum of ISENs 4mA ...

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... PWROK, SVC, SVD Input Logic Low SVC, SVD Leakage NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Gate Driver Timing Diagram PWM t LGFUGR UGATE 1V LGATE ISL6267 = 5V -10°C to +100° SYMBOL TEST CONDITIONS ENABLE SSR V ...

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... PWM pulse is held off until needed. The VW voltage falls as the COMP voltage falls, reducing the current PWM pulse is in 3-phase width. This kind of behavior gives the ISL6267 excellent response DD speed. The fact that all the phases share the same VW window voltage also ensures excellent dynamic current balance among phases ...

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... ENABLE exceeds the logic high threshold. Figure 12 shows the typical start-up timing of VR1 and VR2. The ISL6267 uses digital soft-start to ramp-up DAC to the voltage programmed by the Metal VID. PGOOD is asserted high and low at the end of the ramp up. Similar results occur if ...

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... Interval ENABLE locks pre-Metal VID code. All outputs soft-start to this level. Interval PGOOD signal goes HIGH, indicating proper operation. Interval CPU detects PGOOD high, and drives PWROK high, to allow ISL6267 to prepare for SVI commands. Interval SVC and SVD data lines communicate change in VID code. ...

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... VID code, and the controller soft-starts. VFIX Mode The ISL6267 does not support VFIX Mode. In the event a CPU is not present on a motherboard and the ISL6267 is powered on, the state of SVC and SVD sets the pre-PWROK metal VID as the “Pre-PWROK Metal VID” on page 16 and begins soft-starting. ...

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... NOTE: Indicates a VID not required for AMD Family 10h processors. 18 ISL6267 TABLE 2. SERIAL VID CODES VOLTAGE (V) SVID[6:0] VOLTAGE (V) 1.1500 100_0000b 0.7500 1.1375 100_0001b 0.7375 1.1250 100_0010b 0.7250 1.1125 100_0011b ...

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... Voltage Regulation and Load Line Implementation After the start sequence, the ISL6267 regulates the output voltage to the value set by the VID information, per Table 2. The ISL6267 controls the no-load output voltage to an accuracy of ±0.5% over the range of 0.75V to 1.55V. A differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die ...

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... As the load current increases from zero, the output voltage droops from the VID table value by an amount proportional to the load current, to achieve the load line. The ISL6267 can sense the inductor current through the intrinsic DC Resistance (DCR) of the inductors, as shown in Figures 15 and 16, or through resistors in series with the inductors as shown in Figure 17 ...

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... CCM Switching Frequency The R fset VW windows size and therefore sets the switching frequency. When the ISL6267 is in continuous conduction mode (CCM), the switching frequency is not absolutely constant due to the nature 3 of the R Modulator” on page 14, the effective switching frequency increases during load insertion and decreases during load release to achieve fast response ...

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... ISEN2_NB To Power Stage Tied to 5V ISL6267 Northbridge (NB) VR can be configured for 2- or 1-phase operation. Table 7 shows the Northbridge VR configurations and operational modes, which are programmed by the ISEN2 pin status and the PSI_L command. For 1-phase configuration, tie the ISEN2_NB pin to 5V. ...

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... The controller declares an overvoltage fault and de-asserts PGOOD if the output voltage exceeds the VID set value by +250mV. The ISL6267 immediately declares an OV fault, de-asserts PGOOD, and turn on the low-side power MOSFETs. The low-side power MOSFETs remain on until the output voltage is pulled down below the VID set value when all power MOSFETs are turned off ...

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... Since R o smaller than the rest of the current sensing circuit, the following analysis ignores it. The summed inductor current information is presented to the capacitor C . Equations 18 thru 22 describe the frequency n 24 ISL6267 domain relationship between inductor total current I voltage ntcnet ...

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... FIGURE 21. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS FIGURE 22. LOAD TRANSIENT RESPONSE WHEN C SMALL FIGURE 23. LOAD TRANSIENT RESPONSE WHEN C LARGE 25 ISL6267 (EQ. 23) = 11kΩ correctly n FIGURE 24. OUTPUT VOLTAGE RING-BACK PROBLEM (s) does not accurately is too n FIGURE 25. OPTIONAL CIRCUITS FOR RING-BACK REDUCTION Figure 24 shows the output voltage ring-back problem during load transient response ...

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... NTC network. The recommended values are R = 1kΩ and C sum 26 ISL6267 Overcurrent Protection Refer to Equation 1 on page 20 and Figures 20, 24 and 26; , providing a resistor R sets the droop current change ...

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... T1 is measured after the summing node, and T2 is measured in the voltage loop before the summing node. The spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s) can actually be measured on an ISL6267 regulator. DCR × (EQ. 35) ...

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... NTC thermistor voltage rises. Once the over-temperature threshold is tripped and VR_HOT is taken low, the over-temperature threshold changes to the reset Layout Guidelines Table 9 shows layout considerations for the ISL6267 controller. Refer to the reference designators shown in Figure 31. TABLE 9. LAYOUT CONSIDERATIONS FOR THE ISL6267 CONTROLLER ISL6267 SYMBOL ...

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... TABLE 9. LAYOUT CONSIDERATIONS FOR THE ISL6267 CONTROLLER ISL6267 SYMBOL 1 FB2_NB Place the compensator components (R25, R9, R24, C88, C51, C86, and C153) close to the controller. 2 FB_NB 3 COMP_NB 4 VW_NB Place the capacitor (C85) across VW, and place COMP close to the controller. 5 PGOOD_NB No special consideration. ...

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... TABLE 9. LAYOUT CONSIDERATIONS FOR THE ISL6267 CONTROLLER ISL6267 SYMBOL 21 ISUMN Place the current sensing circuit in general proximity of the controller. Place capacitor Cn very close to the controller. 22 ISUMP Place the NTC thermistor next to VR1 phase-1 inductor (L1 senses the inductor temperature correctly. Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces in parallel fashion with decent width (> ...

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... Place the VSEN/RTN filter (C89, C90) in close proximity to the controller for good decoupling. 46 VSEN_NB 47 ISEN2_NB See ISEN1, ISEN2 and ISEN3 pins for layout guidelines of current-balancing circuit trace routing. 48 ISEN1_NB FIGURE 31. PORTION OF ISL6267EVAL1Z EVALUATION BOARD SCHEMATIC 31 ISL6267 (Continued) LAYOUT GUIDELINES January 31, 2011 FN7801.0 ...

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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 32 ISL6267 www.intersil.com/askourstaff For additional products, see www.intersil.com/product_tree www ...

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... Package Outline Drawing L48.6x6B 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 9/09 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 5. 75 TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 33 ISL6267 48X 0.45 ± 0.10 BOTTOM VIEW MAX 1. SIDE VIEW REF ( 48X 48X DETAIL " ...