ZL2105ALNF Intersil, ZL2105ALNF Datasheet - Page 30

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ZL2105ALNF

Manufacturer Part Number
ZL2105ALNF
Description
IC DGTL DC-DC CTRLR 3A 36QFN
Manufacturer
Intersil
Type
Step-Down (Buck), PWM - Voltage Moder
Datasheet

Specifications of ZL2105ALNF

Internal Switch(s)
Yes
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
0.6 V ~ 5.5 V
Current - Output
3A
Frequency - Switching
200kHz ~ 2MHz
Voltage - Input
4.5 V ~ 14 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
*
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ZL2105ALNF
Manufacturer:
ZILKER
Quantity:
20 000
Selecting the phase offset for the device is
accomplished by selecting a device address according
to the following equation:
For example:
The phase offset of each device may also be set to any
value between 0° and 337.5° in 22.5° increments via
the I
AN2013 for further details.
6.12 Output Sequencing
A group of Zilker Labs devices (both ZL2005 and
ZL2105) may be configured to power up in a
predetermined sequence. This feature is especially
useful when powering advanced processors, FPGAs,
and ASICs that require one supply to reach its
operating voltage prior to another supply reaching its
operating voltage in order to avoid latch-up from
occurring. Multi-device sequencing can be achieved by
configuring each device through the I
interface or by using Zilker Labs patented autonomous
sequencing mode.
Autonomous sequencing mode configures sequencing
by using events transmitted between devices over the
I
device is involved in this method, but the SCL and
SDA pins must be interconnected between all devices
that the user wishes to sequence using this method.
(note: pull-up resistors on SCL and SDA are required
and should be selected using the criteria in the SMBus
2.0 specification).
The sequencing order is determined using each
device’s
autonomous sequencing mode (configured using the
CFG pin), the devices must exhibit sequential device
addresses with no missing addresses in the chain. This
mode will also constrain each device to have a phase
offset according to its device address as described in
Phase Spreading.
The group will turn on in order starting with the device
with the lowest address and will continue through to
2
C/SMBus pins SCL and SDA. No I
2
C/SMBus interface. Refer to Application Note
Phase offset = device address x 45°
A device address of 0x00 or 0x20 would
configure no phase offset
A device address of 0x01 or 0x21 would
configure 45° of phase offset
A device address of 0x02 or 0x22 would
configure 90° of phase offset
I
2
C/SMBus
30
device
2
address.
C or SMBus host
2
C/SMBus
Using
ZL2105
turn on each device in the address chain until all
devices connected have been turned on. When turning
off, the device with the highest address will turn off
first followed in reverse order by the other devices in
the group.
Table 25. CFG Pin Configurations for Sequencing
and Tracking
Sequencing is configured by connecting a resistor from
the CFG pin to ground as described in Table 25. The
CFG pin is used to set the configuration of the SYNC
pin as well as to determine the sequencing method and
order. Refer to Section 5.8 “Switching Frequency and
PLL,” on Page 17 for more details on the operating
parameters of the SYNC pin.
Multiple device sequencing may also be achieved by
issuing PMBus commands to assign the preceding
device in the sequencing chain as well as the device
that will follow in the sequencing chain. This method
places fewer restrictions on device address (no need of
sequential address) and also allows the user to assign
any phase offset to any device irrespective of its device
address.
Note: Event based sequencing and fault spreading are
broadcast in address groups of up to eight Zilker Labs
Digital-DC devices. An address group consists of all
devices whose addresses differ in only the three least
12.1 k
14.7 k
16.2 k
17.8 k
21.5 k
23.7 k
26.1 k
31.6 k
34.8 k
38.3 k
42.2 k
46.4 k
51.1 k
10 k
11 k
R
CFG
Auto detect
Auto detect
Auto detect
Auto detect
Auto detect
SYNC Pin
Config
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
based on device address.
based on device address.
Sequencing and Tracking
Voltage Tracking enabled
sequencing group. Turn-
Device is a last device in
Device is the first device
Sequencing is Disabled.
group. Turn-on order is
group. Turn-on order is
in a nested sequencing
as defined in Table 22.
a nested sequencing
on order is based on
Device is the middle
device in a nested
device address.
Configuration
Sequencing
are disabled
March 30, 2011
FN6851.2

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