ISL6115AEVAL1Z Intersil, ISL6115AEVAL1Z Datasheet - Page 3

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ISL6115AEVAL1Z

Manufacturer Part Number
ISL6115AEVAL1Z
Description
EVAL BOARD 1 FOR ISL6115A
Manufacturer
Intersil
Datasheet

Specifications of ISL6115AEVAL1Z

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Pin Descriptions
PIN
NO.
1
2
3
4
5
6
7
8
SYMBOL
PGOOD
PWRON
GATE
ISEN
CTIM
ISET
VDD
VSS
Current Set
Current Sense
External FET Gate
Drive Pin
Chip Return
Chip Supply
Current Limit Timing
Capacitor
Power Good Indicator Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open
Power-ON
FUNCTION
3
Connect to the low side of the current sense resistor through the current limiting set resistor.
Connect to the more positive end of sense resistor to measure the voltage drop across this
This pin functions as the current limit programming pin.
resistor.
Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to
ground sets the turn-on ramp. At turn-on this capacitor will be charged to V
by an 14µA current source.
12V chip supply. This can be either connected directly to the +12V rail supplying the
switched load voltage or to a dedicated V
Connect a capacitor from this pin to ground. This capacitor determines the time delay
between an overcurrent event and chip output shutdown (current limit time-out). The
duration of current limit time-out is equal to 93kΩ x C
drain N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less than
the UV level for the particular IC.
PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is
driven high to a maximum of 5V or is left open. Do not drive this input >5V. After a
current limit time-out, the chip is reset by a low level signal applied to this pin. This input
has 20µA pull-up capability.
ISL6115A
DESCRIPTION
SS
+12V supply.
TIM
.
April 23, 2010
DD
FN6855.1
+6.5V

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