DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 16

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

5–2
Using the Board Test System
MAX V CPLD Development Kit User Guide
The Config Menu
The GPIO Tab
1
1
A GUI appears, displaying the application tab that corresponds to the design running
in the CPLD.
This section describes each control in the Board Test System application.
Each design example tests a different functionality that corresponds to one or more
application tabs. Use the Config menu to select the design you want to use.
shows the Config menu.
Figure 5–1. The Config Menu
To configure the CPLD with a test system design, on the Config menu, click the
configure command that corresponds to the functionality you wish to test.
While the configuration is running, a progress bar displays. A message shows when
the configuration is completed.
The GPIO tab allows you to interact with all the general purpose user I/O
components on your board.
The MAX V CPLD Development Kit includes three designs examples for the GPIO
tab
■
■
■
BTS General (VAR_VCCIO = 3.3V) runs when I/O voltage is set to 3.3 V (Bank 2).
BTS General (VAR_VCCIO = 2.5V) runs when I/O voltage is set to 2.5 V (Bank 2).
BTS General (VAR_VCCIO = 1.8V) runs when I/O voltage is set to 1.8 V (Bank 2).
(Figure
5–1):
January 2011 Altera Corporation
Chapter 5: Board Test System
Using the Board Test System
Figure 5–1