DC1437B-AB Linear Technology, DC1437B-AB Datasheet - Page 11

• Manufacturer Part Number: DC1437B-AB
• Description: BOARD EVAL LTM9003-AB
• Manufacturer: Linear Technology
• Type: Pre-Distortion Receiver Subsystemr

Specifications of DC1437B-AB

• Design Resources: DC1437 Schematic
• Frequency: 184MHz
• Features: LTM9003 12bit Predistortion Receiver Subsystem, LVDS Output
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Mcu Supported Families: LTM9003
• Development Tool Type: Hardware - Eval/Demo Board
• For Use With/related Products: LTM9003
• Lead Free Status / RoHS Status: Not applicable / Not applicable

pin FuncTions
V
(LTM9003-AB) Supply Voltage for the Mixer. V
internally bypassed to GND.
V
V
V
V
OV
Drivers. OV
GND (See Table for Locations): Module Ground.
OGND (Pins F12, H8, H10, H12, J12): Output Driver
Ground.
RF (Pin G1): Single-Ended Input for the RF Signal. This
pin is internally connected to the primary side of the RF
input transformer, which has low DC resistance to ground.
If the RF source is not DC blocked, then a series blocking
capacitor must be used. The RF input is internally matched
from 1.1GHz to 1.8GHz. Operation down to 400MHz or up
to 3.8GHz is possible with simple external matching.
LO (Pin J2): Single-Ended Input for the Local Oscillator
Signal. This pin is internally connected to the primary side
of the LO transformer, which is internally DC blocked. An
external blocking capacitor is not required. The LO input is
internally matched from 0.9GHz to 3.5GHz. Operation down
to 380MHz is possible with simple external matching.
MIX_EN (Pin F4): Mixer Enable Pin. Connecting MIX_EN
to V
to GND disables the mixer. The MIX_EN pin should not
be left floating.
AMP_EN (Pin C3): Amplifier Enable Pin. This pin is
internally pulled high by a typically 30k resistor to V
Connecting AMP_EN to V
Connecting AMP_EN to GND disables the amplifier.
ENC
the positive edge.
ENC
sion starts on the negative edge. Bypass to ground with
0.1µF ceramic for single-ended ENCODE signal.
CC1
CC2
CC2
DD
DD
DD
CC1
+
–
is internally bypassed to GND.
(Pins D11, E7, E8): 2.5V Supply Voltage for ADC.
(Pins B1, B2): 3.3V Supply Voltage for the Amplifier.
is internally bypassed to GND.
(Pin D12): ADC Encode Input. Conversion starts on
(Pin E12): ADC Encode Complement Input. Conver-
(Pins E1, E2, F2): 3.3V (LTM9003-AA) or 5V
(Pins G12, H9, H11): 2.5V Supply for the Output
results in normal operation. Connecting MIX_EN
DD
is internally bypassed to OGND.
CC2
results in normal operation.
CC1
CC2
is
.
SHDN (Pin B11): ADC Shutdown Mode Selection Pin. Con-
necting SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to V
outputs at high impedance. Connecting SHDN to V
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to V
in sleep mode with the outputs at high impedance.
OE (Pin C11): Output Enable Pin. Refer to SHDN pin
function.
MODE (Pin C7): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
offset binary output format and turns the clock duty cycle
stabilizer off. 1/3 V
and turns the clock duty cycle stabilizer on. 2/3 V
2’s complement output format and turns the clock duty
cycle stabilizer on. V
format and turns the clock duty cycle stabilizer off.
SENSE (Pin G7): Reference Programming Pin. Connecting
SENSE to 1.25V selects the internal reference and a ±0.5V
input range. V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±V
LVDS (Pin D7): Output Mode Selection Pin. Connect LVDS
to V
Digital Outputs
D0
Digital Outputs. All LVDS outputs require differential 100Ω
termination resistors at the LVDS receiver. D11
the MSB.
CLKOUT
Output. Latch data on rising edge of CLKOUT
edge of CLKOUT
OF
High when an over or under flow has occurred.
SENSE
–
–
/D0
/OF
DD
.
+
+
. ±1V is the largest valid input range.
–
– D11
(Pins E5/F5): LVDS Over/Under Flow Output.
/CLKOUT
DD
–
/D11
+
selects the internal reference and a ±1V
DD
.
DD
+
results in normal operation with the
+
(Pins J10/J11): LVDS Data Valid
DD
selects offset binary output format
(See Table for Locations): LVDS
selects 2’s complement output
DD
and OE to V
LTM9003
DD
DD
–
–
/D11
, falling

selects
DD
results
and
+
9003f
is