DC1437B-AB Linear Technology, DC1437B-AB Datasheet - Page 20

• Manufacturer Part Number: DC1437B-AB
• Description: BOARD EVAL LTM9003-AB
• Manufacturer: Linear Technology
• Type: Pre-Distortion Receiver Subsystemr

Specifications of DC1437B-AB

• Design Resources: DC1437 Schematic
• Frequency: 184MHz
• Features: LTM9003 12bit Predistortion Receiver Subsystem, LVDS Output
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Mcu Supported Families: LTM9003
• Development Tool Type: Hardware - Eval/Demo Board
• For Use With/related Products: LTM9003
• Lead Free Status / RoHS Status: Not applicable / Not applicable

LTM9003
termination resistor, even if the signal is not used (such as
OF
board traces for each LVDS output pair should be routed
close together. To minimize clock skew all LVDS PC board
traces should have about the same length.
Data Format
The LTM9003 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MODE pin. Connecting MODE to GND
or 1/3V
MODE to 2/3V
format. An external resistor divider can be used to set the
1/3V
states for the MODE pin.
Table 4. MODE Pin Function
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. A differential logic high on
the OF
Output Clock
The LTM9003 has a delayed version of the ENC
able as a digital output, CLKOUT. The CLKOUT pin can be
used to synchronize the converter data to the digital system.
This is necessary when using a sinusoidal encode. Data
will be updated just after CLKOUT
be latched on the falling edge of CLKOUT
Output Driver Power
OV
should be connected to GND.
applicaTions inForMaTion
0
+
DD
/OF
MODE PIN
DD
1/3V
2/3V
should be connected to a 2.5V supply and OGND
+
V
–
DD
/OF
0
DD
or 2/3V
or CLKOUT
DD
DD
selects offset binary output format. Connecting
–
pins indicates an overflow or underflow.
DD
DD
or V
logic values. Table 4 shows the logic
+
OUTPUT FORMAT
2’s Complement
2’s Complement
/CLKOUT
Straight Binary
Straight Binary
DD
selects 2’s complement output
–
). To minimize noise the PC
+
/CLKOUT
CLOCK DUTY CYCLE
+
STABILIZER
/CLKOUT
–
rises and can
+
Off
On
Off
On
input avail-
–
.
Output Enable
The outputs may be disabled with the output enable
pin, OE. In LVDS output mode OE high disables all data
outputs including OF and CLKOUT. The data access and
bus relinquish times are too slow to allow the outputs to
be enabled and disabled during full speed operation. The
output Hi-Z state is intended for use during long periods
of inactivity.
The Hi-Z state is not a truly open circuit; the output pins
that make an LVDS output pair have a 20k resistance
between them.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to V
results in sleep mode, which powers down all circuitry
including the reference and the ADC typically dissipates
1.5mW. When exiting sleep mode, it will take milliseconds
for the output data to become valid because the reference
capacitors have to recharge and stabilize. Connecting
SHDN to V
ADC typically dissipates 30mW. In nap mode, the on-chip
reference circuit is kept on, so that recovery from nap
mode is faster than that from sleep mode, typically taking
100 clock cycles. In both sleep and nap modes, all digital
outputs are disabled and enter the Hi-Z state.
Supply Sequencing
The V
and amplifier, respectively, and the V
supply to the ADC. The mixer, amplifier and ADC are sepa-
rate integrated circuits within the LTM9003. Separate linear
regulators can be used without additional supply sequenc-
ing circuitry if they have common input supplies.
CC1
and V
DD
and OE to GND results in nap mode and the
CC2
pins provide the supply to the mixer
DD
DD
pin provides the
and OE to V
9003f
DD