DC1398A-GA Linear Technology, DC1398A-GA Datasheet - Page 16

• Manufacturer Part Number: DC1398A-GA
• Description: BOARD EVAL LTM9001-GA
• Manufacturer: Linear Technology
• Type: Baseband Receiverr

Specifications of DC1398A-GA

• Design Resources: Demo Circuit 1398A Schematic
• Frequency: 0Hz ~ 300MHz
• Kit Contents: Board, Manual
• Features: LTM9001 16bit Receiver Subsystem, DC-10MHz LPF
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Development Tool Type: Hardware - Eval/Demo Board
• Mcu Supported Families: LTM9001
• For Use With/related Products: LTM9001
• Lead Free Status / RoHS Status: Not applicable / Not applicable

APPLICATIONS INFORMATION
LTM9001-GA
PGA Pin
The PGA pin selects between two gain settings for the
ADC front-end. PGA = low selects the maximum input
span; PGA = high selects a 3.5dB lower input span. The
high input range has the best SNR. For applications with
high linearity requirements, the low input range will have
improved distortion; however, the SNR will be 1.8dB worse.
See the Typical Performance Characteristics section.
Driving the Clock or Encode Inputs
Certain versions of LTM9001 have differential encode
inputs, others have a single-ended clock input.The noise
performance of the converter can depend on the encode
signal quality as much as the analog input. The encode
inputs are intended to be driven differentially, primarily for
noise immunity from common mode noise sources. Each
input is biased through a 6k resistor to a 1.6V bias. The
bias resistors set the DC operating point for transformer
coupled drive circuits and can set the logic threshold for
single-ended drive circuits.
Any noise present on the encode signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter. In applications where jitter is critical (high
input frequencies), take the following into consideration:
1. Differential drive should be used.
2. Use the largest amplitude possible. If using transformer
3. If the ADC is clocked with a fi xed frequency sinusoidal
4. Balance the capacitance and series resistance at both
The encode inputs have a common mode range of 1.2V
to V
single-ended drive.
The encode clock inputs have a differential 100Ω input
impedance. For 50Ω inputs e.g. signal generators, an
additional 100Ω impedance will provide an impedance
match, as shown in Figure 7b.
16
coupling, use a higher turns ratio to increase the
amplitude.
signal, fi lter the encode signal to reduce wideband
noise.
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
DD
. Each input may be driven from ground to V
DD
for
The single-ended CLK input on LTM9001-GA can be driven
directly with a CMOS or TTL level signal. A sinusoidal clock
can be used along with a low-jitter squaring circuit before
the CLK pin (Figure 8).
ENC
ENC –
+
SINUSOIDAL
0.1μF
0.1μF
Figure 8. Sinusoidal Single-Ended CLK Drive
CLOCK
INPUT
Figure 7a. Equivalent Encode Input Circuit
100Ω
T1 = M/A-COM ETC1-1-13
Figure 7b. Transformer Driven Encode
LTM9001-TBD
T1
56Ω
V
4.7μF
0.1μF
DD
V
1k
DD
50Ω
50Ω
1.6V
1k
6k
NC7SVU04
1.6V
6k
V
DD
0.1μF
8.2pF
FERRITE
0.1μF
BEAD
CLK
CLEAN 3.3V
LTM9001-GA
SUPPLY
100Ω
LTM9001-TBD
TO INTERNAL
ADC CLOCK
ENC
DRIVERS
ENC –
9001-GA F09a
+
9001-GA F07b
9001-GA F07a
9001gaf