DC1398A-GA Linear Technology, DC1398A-GA Datasheet - Page 17

• Manufacturer Part Number: DC1398A-GA
• Description: BOARD EVAL LTM9001-GA
• Manufacturer: Linear Technology
• Type: Baseband Receiverr

Specifications of DC1398A-GA

• Design Resources: Demo Circuit 1398A Schematic
• Frequency: 0Hz ~ 300MHz
• Kit Contents: Board, Manual
• Features: LTM9001 16bit Receiver Subsystem, DC-10MHz LPF
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Development Tool Type: Hardware - Eval/Demo Board
• Mcu Supported Families: LTM9001
• For Use With/related Products: LTM9001
• Lead Free Status / RoHS Status: Not applicable / Not applicable

APPLICATIONS INFORMATION
Maximum and Minimum Encode Rates
The maximum encode rate for the LTM9001-GA is 25Msps.
For the ADC to operate properly the CLK signal should
have a 50% (±5%) duty cycle. Each half cycle must have
at least 18.9ns (LTM9001-GA) for the ADC internal circuitry
to have enough settling time for proper operation.
An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of CLK or ENC to sample the analog
input. The falling edge of CLK or ENC is ignored and an
internal falling edge is generated by a phase-locked loop.
The input clock duty cycle can vary from 30% to 70%
and the clock duty cycle stabilizer will maintain a constant
50% internal duty cycle. If the clock is turned off for a
long period of time, the duty cycle stabilizer circuit will
require one hundred clock cycles for the PLL to lock onto
the input clock. To use the clock duty cycle stabilizer, the
MODE pin must be connected to 1/3V
external resistors.
The lower limit of the sample rate is determined by the
droop of the sample and hold circuits. The pipelined
architecture of this ADC relies on storing analog signals
on small valued capacitors. Junction leakage will discharge
the capacitors. The specifi ed minimum operating frequency
for the LTM9001 is 1Msps.
DD
or 2/3V
DD
using
DIGITAL OUTPUTS
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer in CMOS mode. Each buffer is powered by OV
and OGND, isolated from the ADC power and ground. The
additional N-channel transistor in the output driver allows
operation down to low voltages. The internal resistor in
series with the output makes the output appear as 50Ω
to external circuitry and eliminates the need for external
damping resistors.
LATCH
FROM
DATA
Figure 9. Equivalent Circuit for a Digital Output Buffer
PREDRIVER
LOGIC
V
DD
V
DD
LTM9001-GA
LTM9001-GA
OV
DD
9001-GA F10
43Ω
OV
OGND
DD
17
TYPICAL
DATA
OUTPUT
0.5V
TO 3.6V
9001gaf
DD