LIS302DLH STMicroelectronics, LIS302DLH Datasheet - Page 23

SENSOR ACCELEROMETER 3AXIS 14LGA

LIS302DLH

Manufacturer Part Number
LIS302DLH
Description
SENSOR ACCELEROMETER 3AXIS 14LGA
Manufacturer
STMicroelectronics
Datasheet

Specifications of LIS302DLH

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Axis
X, Y, Z
Acceleration Range
±2.3g, 9.2g
Sensitivity
18mg/digit, 72mg/digit
Voltage - Supply
2.16 V ~ 3.6 V
Output Type
Digital
Bandwidth
100Hz ~ 400Hz Selectable
Interface
I²C, SPI
Mounting Type
Surface Mount
Package / Case
14-LGA
Package Type
LGA
Operating Supply Voltage (min)
2.16V
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (max)
3.6V
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Product Depth (mm)
3mm
Product Height (mm)
0.92mm
Product Length (mm)
5mm
Mounting
Surface Mount
Pin Count
14
Sensing Axis
Triple
Acceleration
2 g, 4 g, 8 g
Digital Output - Number Of Bits
16 bit
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.16 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Digital Output - Bus Interface
I2C, SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-10052

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LIS302DLH
6
Register mapping
The table given below provides a listing of the 8 bit registers embedded in the device and
the related addresses:
Table 15.
Registers marked as Reserved must not be changed. The writing to those registers may
cause permanent damages to the device.
Reserved (do not modify)
WHO_AM_I
Reserved (do not modify)
CTRL_REG1
CTRL_REG2
CTRL_REG3
CTRL_REG4
CTRL_REG5
HP_FILTER_RESET
REFERENCE
STATUS_REG
OUT_X_L
OUT_X_H
OUT_Y_L
OUT_Y_H
OUT_Z_L
OUT_Z_H
Reserved (do not modify)
INT1_CFG
INT1_SOURCE
INT1_THS
INT1_DURATION
INT2_CFG
INT2_SOURCE
INT2_THS
INT2_DURATION
Reserved (do not modify)
Register address map
Name
Doc ID 15797 Rev 1
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
r
r
r
r
r
r
r
r
r
r
Register address
00 - 0E
2E - 2F
10 - 1F
38 - 3F
Hex
2A
2B
2C
2D
0F
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
000 1111 00110010 Dummy register
010 0000 00000111
010 0001 00000000
010 0010 00000000
010 0011 00000000
010 0100 00000000
010 0101
010 0110 00000000
010 0111 00000000
010 1000
010 1001
010 1010
010 1011
010 1100
010 1101
011 0000 00000000
011 0001 00000000
011 0010 00000000
011 0011 00000000
011 0100 00000000
011 0101 00000000
011 0110 00000000
011 0111 00000000
Binary
Default
output
output
output
output
output
output
Register mapping
Reserved
Reserved
Dummy register
Reserved
Reserved
Comment
23/37

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