LAN9215-MT SMSC, LAN9215-MT Datasheet - Page 126

CONTROLLER, ENET, NON-PCI, 100TQFP

LAN9215-MT

Manufacturer Part Number
LAN9215-MT
Description
CONTROLLER, ENET, NON-PCI, 100TQFP
Manufacturer
SMSC
Datasheets

Specifications of LAN9215-MT

Data Rate
100Mbps
No. Of Ports
2
Ethernet Type
IEEE 802.3 / 802.3u
Supply Current
40mA
Supply Voltage Range
2.97V To 3.63V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
TQFP
Interface Type
HBI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Revision 1.2 (03-29-06)
6.6
SYMBOL
SYMBOL
t
t
cycle
t
t
t
t
t
t
doh
csh
asu
dsu
csl
ah
dh
nCS, nRD
Data Bus
A[7:1]
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
PIO writes are used for all LAN9215 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
Note: The “Data Bus” width is 16 bits
PIO Writes
DESCRIPTION
Data Output Hold Time
DESCRIPTION
Write Cycle Time
nCS, nWR Deassertion Time (see Note below)
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
nCS, nWR Assertion Time
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing
Figure 6.5 PIO Write Cycle Timing
Table 6.7 PIO Write Cycle Timing
DATASHEET
126
Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX
MIN
MIN
165
32
13
0
0
7
0
0
TYP
TYP
133
MAX
MAX
SMSC LAN9215
Datasheet
UNITS
UNITS
ns
ns
ns
ns
ns
ns
ns
ns

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