LAN9215-MT SMSC, LAN9215-MT Datasheet - Page 29

• Manufacturer Part Number: LAN9215-MT
• Description: CONTROLLER, ENET, NON-PCI, 100TQFP
• Manufacturer: SMSC

Specifications of LAN9215-MT

• Data Rate: 100Mbps
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Supply Current: 40mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• Interface Type: HBI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX
SMSC LAN9215
3.6
3.6.1
3.6.2
3.7
3.8
Destination Address Source Address ……………FF FF FF FF FF FF
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
…CRC
It should be noted that Magic Packet detection can be performed when LAN9215 is in the D0 or D1
power states. In the D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the
D1 state, Magic Packet detection, as well as wake-up frame detection, are automatically enabled when
the device enters the D1 state.
Bus Writes
The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit write). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next write is performed to the other word. If a write to the
same word is performed, the LAN9215 disregards the transfer.
Bus Reads
The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit read). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next read is performed from the other word. If a read to the
same word is performed, the data read is invalid and should be re-read. This is not a fatal error. The
LAN9215 will reset its read counters and restart a new cycle on the next read.
TheLAN9215supports “Big-” or “Little-Endian” processorsTo support big-endian processors, the
hardware designer must explicitly invert the layout of the byte lanes.
Internally the LAN9215 is 32-bits wide.The LAN9215 supports a Word Swap Function . This feature is
controlled by the Word Swap Register, which is described in
Swap Control," on page
Controls and Status Registers and the Transmit and Receive Data FIFOs. Refer to
Swap Control"
Host Bus Operations
Big and Little Endian Support
Word Swap Function
below for more details. Whenever the LAN9215 transmits data from the Transmit Data
91. This register affects how words on the data bus are written to or read from
DATASHEET
29
Section 5.3.17, "WORD SWAP—Word
Revision 1.2 (03-29-06)
Table 3.7, "Word