UBA2028T/N1 NXP Semiconductors, UBA2028T/N1 Datasheet - Page 6

• Manufacturer Part Number: UBA2028T/N1
• Description: CFL DRIVER, 600V, DIMMABLE, 20SOIC
• Manufacturer: NXP Semiconductors

Specifications of UBA2028T/N1

• Module Configuration: Half Bridge
• Supply Current: 170µA
• Meter Display Type: Fluorescent Lamp
• Supply Voltage Range: 8.6V To 9.6V, 12.4V To 13.6V
• Driver Case Style: SOIC
• No. Of Pins: 20
• Operating: RoHS Compliant

NXP Semiconductors
8. Functional description
UBA2028
Product data sheet
8.1 Start-up state
8.2 Oscillation
8.3 Adaptive non-overlap
8.4 Timing circuit
Initial start-up can be achieved by charging the low voltage supply capacitor at pin 16 (see
Figure 8
under the condition that both half-bridge transistors TR1 and TR2 are non-conductive.
The circuit will be reset in the start-up state. If the low voltage supply (V
value of V
High-Side (HS) driver. Below the lockout voltage at the FS pin the output voltage (TR1
gate voltage − V
state.
The internal oscillator is a Voltage Controlled Oscillator (VCO) circuit which generates a
sawtooth waveform between the V
determined by capacitor C
and maximum switching frequencies are determined by R
internally fixed. The sawtooth frequency is twice the half-bridge frequency. The UBA2028
brings the transistors TR1 and TR2 into conduction alternately with a duty cycle of
approximately 50 %. An overview of the oscillator signal and driver signals is illustrated in
Figure
Low-Side (LS) transistor (TR2) is switched on. The first conducting time is made extra
long to enable the bootstrap capacitor to charge.
The non-overlap time is realized with an adaptive non-overlap timing circuit (ANT). By
using an adaptive non-overlap circuit, the application can determine the duration of the
non-overlap time and make it optimum for each frequency; see
time is determined by the slope of the half-bridge voltage, and is detected by the signal
across resistor R15 see
The minimum non-overlap time is internally fixed. The maximum non-overlap time is
internally fixed at approximately 25 % of the bridge period time. An internal filter of 30 ns
is included at the ACM pin to increase the noise immunity.
A timing circuit is included to determine the preheat time and the ignition time. The circuit
consists of a clock generator and a counter.
The preheat time is defined by C
of 7 pulses at C
operating after the start-up state, as soon as the low supply voltage (V
V
timer is not operating C
DD(startup)
7. The oscillator starts oscillating at f
and
DD(startup)
or when a critical value of the lamp voltage (V
Figure
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CT
SH
; the maximum ignition time is 1 pulse at C
) is zero. The voltages at pins CF and CT are zero during the start-up
the circuit will start oscillating. A DC reset circuit is incorporated in the
9) via an external start-up resistor. Start-up of the circuit is achieved
CT
Rev. 02 — 19 July 2010
Figure 8
is discharged to 0 V at 1 mA.
CF
, resistor R
600 V dimmable power IC for compact fluorescent lamps
CT
(R6 in
o(osc)max
and R
IREF
Figure
IREF
level and 0 V. The frequency of the sawtooth is
, and the voltage at pin CSW. The minimum
max
connected to pins 10 and 13, and consists
. During the first switching cycle the
9) which is connected directly to pin ACM.
lamp(fail)
IREF
CT
and C
. The timing circuit starts
Figure
) is exceeded. When the
CF
UBA2028
7. The non-overlap
DD
; their ratio is
© NXP B.V. 2010. All rights reserved.
DD
) has reached
) reaches the
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