SC16C554BIB80 NXP Semiconductors, SC16C554BIB80 Datasheet - Page 31

• Manufacturer Part Number: SC16C554BIB80
• Description: IC, UART, QUAD, 16BYTE FIFO, 16C554
• Manufacturer: NXP Semiconductors

Specifications of SC16C554BIB80

• No. Of Channels: 4
• Data Rate: 5Mbps
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 80
• Svhc: No SVHC (18-Jun-2010)
• Uart Features: Pin & Software Compatible, 16-Byte Transmit FIFO, Automatic Hardware Flow Control
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
SC16C554B_554DB
Product data sheet
7.4 Interrupt Status Register (ISR)
Table 12.
The SC16C554B/554DB provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged until
the pending interrupt is serviced. Whenever the Interrupt Status Register is read, the
interrupt status is cleared. However, it should be noted that only the current pending
interrupt is cleared by the read. A lower level interrupt may be seen after re-reading the
interrupt status bits.
four prioritized interrupt levels and the interrupt sources associated with each of these
interrupt levels.
Table 13.
Table 14.
FCR[7]
0
0
1
1
Priority
level
1
2
2
3
4
Bit
7:6
5:4
3:1
0
ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt
0
0
0
0
0
RCVR trigger levels
Interrupt source
Interrupt Status Register bits description
ISR[7:6]
ISR[3:1]
Symbol
ISR[5:4]
ISR[0]
FCR[6]
0
1
0
1
All information provided in this document is subject to legal disclaimers.
0
0
0
0
0
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Table 13 “Interrupt source”
Rev. 4 — 8 June 2010
0
0
1
0
0
FIFOs enabled. These bits are set to a logic 0 when the FIFO is not
INT priority bits 2 to 0. These bits indicate the source for a pending
Description
being used. They are set to a logic 1 when the FIFOs are enabled.
Reserved; set to 0.
interrupt at interrupt priority levels 1, 2, and 3 (see
INT status.
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 = an interrupt is pending and the ISR contents may be used
as a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
RX FIFO trigger level
1
4
8
14
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
shows the data values (bits 0 to 5) for the
SC16C554B/554DB
LSR (Receiver Line Status Register)
RXRDY (Receive Data Ready)
RXRDY (Receive Data time-out)
TXRDY (Transmitter Holding
MSR (Modem Status Register)
Register Empty)
© NXP B.V. 2010. All rights reserved.
Table
13).
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