SC16C650BIB48 NXP Semiconductors, SC16C650BIB48 Datasheet - Page 10

• Manufacturer Part Number: SC16C650BIB48
• Description: UART, 32BYTE FIFO, 16C650, LQFP48
• Manufacturer: NXP Semiconductors

Specifications of SC16C650BIB48

• No. Of Channels: 1
• Data Rate: 3Mbps
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Operating: RoHS Compliant
• Uart Features: Automatic Software/Hardware Flow Control, Programmable Xon/Xoff Characters
• Rohs Compliant: Yes

NXP Semiconductors
SC16C650B_4
Product data sheet
6.3 Hardware flow control
6.4 Software flow control
data is delivered to the external CPU. An interrupt is generated whenever the Receive
Holding Register (RHR) has not been read following the loading of a character or the
receive trigger level has not been reached.
Table 4.
When automatic hardware flow control is enabled, the SC16C650B monitors the CTS pin
for a remote buffer overflow indication and controls the RTS pin for local buffer overflows.
Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to
a logic 1. If CTS changes from a logic 0 to a logic 1 indicating a flow control request,
ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the SC16C650B will suspend
TX transmissions as soon as the stop bit of the character in process is shifted out.
Transmission is resumed after the CTS input returns to a logic 0, indicating more data may
be sent.
With the auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1 (RTS
off), until the receive FIFO reaches the next trigger level. However, the RTS pin will return
to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the
programmed trigger level. However, under the above described conditions, the
SC16C650B will continue to accept data until the receive FIFO is full.
When software flow control is enabled, the SC16C650B compares one or two sequential
receive data characters with the programmed Xon or Xoff character value(s). If received
character(s) match the programmed Xoff values, the SC16C650B will halt transmission
(TX) as soon as the current character(s) has completed transmission. When a match
occurs, the receive ready (if enabled via Xoff IER[5]) flags will be set and the interrupt
output pin (if receive interrupt is enabled) will be activated. Following a suspension due to
a match of the Xoff characters’ values, the SC16C650B will monitor the receive data
stream for a match to the Xon1, Xon2 character value(s). If a match is found, the
SC16C650B will resume operation and clear the flags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions. When double 8-bit Xon/Xoff characters are selected, the SC16C650B
compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above
described flow control mechanisms, flow control characters are not placed (stacked) in the
user accessible RX data buffer or FIFO. When using a software flow control the Xon/Xoff
characters cannot be used for data transfer.
Selected trigger level
(characters)
8
16
24
28
Flow control mechanism
Rev. 04 — 14 September 2009
INT pin activation
8
16
24
28
UART with 32-byte FIFOs and IrDA encoder/decoder
Negate RTS or
send Xoff
8
16
24
28
SC16C650B
Assert RTS or
send Xon
0
7
15
23
© NXP B.V. 2009. All rights reserved.
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