DSPIC30F4012-20I/SO Microchip Technology, DSPIC30F4012-20I/SO Datasheet - Page 142

• Manufacturer Part Number: DSPIC30F4012-20I/SO
• Description: IC, DSC, 16BIT, 48KB 20MHZ, 5.5V, SOIC28
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F4012-20I/SO

• Core Frequency: 20MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 20
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401220ISO

dsPIC30F4011/4012
20.4
The conversion trigger terminates acquisition and starts
the requested conversions.
The SSRC<2:0> bits select the source of the
conversion trigger.
The SSRC bits provide for up to five alternate sources
of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit causes
the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the con-
version trigger is under A/D clock control. The SAMC
bits select the number of A/D clocks between the start
of acquisition and the start of conversion. This provides
the fastest conversion rates on multiple channels.
SAMC must always be at least one clock cycle.
Other trigger sources can come from timer modules,
motor control PWM module or external interrupts.
20.5
Clearing the ADON bit during a conversion aborts the
current conversion and stops the sampling sequencing.
The ADCBUFx is not updated with the partially com-
pleted A/D conversion sample. That is, the ADCBUFx
will continue to contain the value of the last completed
conversion (or the last value written to the ADCBUFx
register).
If the clearing of the ADON bit coincides with an
auto-start, the clearing has a higher priority.
After the A/D conversion is aborted, a 2 T
required before the next sampling may be started by
setting the SAMP bit.
If sequential sampling is specified, the A/D continues at
the next sample pulse, which corresponds with the next
channel converted. If simultaneous sampling is speci-
fied, the A/D continues with the next multichannel
group conversion sequence.
DS70135G-page 142
Note:
Programming the Start of the
Conversion Trigger
Aborting a Conversion
To operate the ADC at the maximum
specified conversion speed, the auto-
convert trigger option should be selected
(SSRC = 111) and the auto-sample
time
(SAMC = 00001). This configuration gives
a total conversion period (sample +
convert) of 13 T
The use of any other conversion trigger
results in additional T
synchronize the external event to the
ADC.
bits should be set to ‘1’ T
AD
.
AD
cycles to
AD
wait is
AD
20.6
The A/D conversion requires 12 T
A/D conversion clock is software selected using a 6-bit
counter. There are 64 possible options for T
EQUATION 20-1:
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(T
of 83.33 nsec (for V
“Electrical Characteristics”
other operating conditions.
Example 20-1
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 20-1:
AD
) must be selected to ensure a minimum T
Therefore,
Set ADCS<5:0> = 9
Selecting the A/D Conversion
Clock
T
ADCS<5:0> = 2
Actual T
AD
= T
ADCS<5:0> = 2
shows a sample calculation for the
CY
AD
T
T
* (0.5 * (ADCS<5:0> + 1))
AD
CY
DD
=
= 2 •
= 8.33
=
= 165 nsec
A/D CONVERSION CLOCK
A/D CONVERSION CLOCK
CALCULATION
= 33 nsec (30 MIPS)
= 154 nsec
© 2010 Microchip Technology Inc.
= 5V). Refer to
T
33 nsec
T
T
CY
2
AD
CY
154 nsec
2
33 nsec
for minimum T
(ADCS<5:0> + 1)
T
T
AD
– 1
CY
AD
(9 + 1)
. The source of the
– 1
– 1
Section 24.0
AD
AD
.
AD
under
time